Seema Khowala 2e912e13d0 gpu: nvgpu: priv_ring MISRA fix for rule 10.3 ...

JIRA NVGPU-3288

Change-Id: Icf0b91de37408be2c3d28c3cd442d2e4af2e13d1
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110651
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2019-05-03 14:05:21 -07:00

..

priv_ring_gm20b.c

gpu: nvgpu: add cg and pg function

2019-03-08 16:24:35 -08:00

priv_ring_gm20b.h

gpu: nvgpu: remove hw_pri_ringmaster_*.h header include from gr_gk20a.c

2019-03-05 03:48:08 -08:00

priv_ring_gp10b.c

gpu: nvgpu: priv_ring MISRA fix for rule 10.3

2019-05-03 14:05:21 -07:00

priv_ring_gp10b.h

gpu: nvgpu: move chip specific priv_ring to hal

2019-02-27 13:43:47 -08:00