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88c8baa29f
Create common.hal.regops unit by moving all regops chip files under hal/ directory Update Makefiles and include paths accordingly Jira NVGPU-2037 Change-Id: Iac1833b8916d919f7d448d17f5dd7a853760f55c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2094288 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
42 lines
1.9 KiB
C
42 lines
1.9 KiB
C
/*
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*
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* Tegra GK20A GPU Debugger Driver Register Ops
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*
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* Copyright (c) 2013-2019 NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_REGOPS_GM20B_H
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#define NVGPU_REGOPS_GM20B_H
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const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void);
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u64 gm20b_get_global_whitelist_ranges_count(void);
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const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void);
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u64 gm20b_get_context_whitelist_ranges_count(void);
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const u32 *gm20b_get_runcontrol_whitelist(void);
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u64 gm20b_get_runcontrol_whitelist_count(void);
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const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void);
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u64 gm20b_get_runcontrol_whitelist_ranges_count(void);
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const u32 *gm20b_get_qctl_whitelist(void);
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u64 gm20b_get_qctl_whitelist_count(void);
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const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void);
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u64 gm20b_get_qctl_whitelist_ranges_count(void);
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#endif /* NVGPU_REGOPS_GM20B_H */
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