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b17d9708c9
JIRA DNVGPU-45 Change-Id: I237ce81e31b036c05c82d46eea8694ffe1c2e3df Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1205849 (cherry picked from commit 9a4006f76b75a8ad525e7aa5ad1f609aaae49126) Reviewed-on: http://git-master/r/1227256 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
89 lines
3.1 KiB
C
89 lines
3.1 KiB
C
/*
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* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2015-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef _ctrlclkavfs_h_
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#define _ctrlclkavfs_h_
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#include "ctrlboardobj.h"
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/*!
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* Valid global VIN ID values
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*/
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#define CTRL_CLK_VIN_ID_SYS 0x00000000
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#define CTRL_CLK_VIN_ID_LTC 0x00000001
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#define CTRL_CLK_VIN_ID_XBAR 0x00000002
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#define CTRL_CLK_VIN_ID_GPC0 0x00000003
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#define CTRL_CLK_VIN_ID_GPC1 0x00000004
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#define CTRL_CLK_VIN_ID_GPC2 0x00000005
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#define CTRL_CLK_VIN_ID_GPC3 0x00000006
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#define CTRL_CLK_VIN_ID_GPC4 0x00000007
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#define CTRL_CLK_VIN_ID_GPC5 0x00000008
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#define CTRL_CLK_VIN_ID_GPCS 0x00000009
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#define CTRL_CLK_VIN_ID_SRAM 0x0000000A
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#define CTRL_CLK_VIN_ID_UNDEFINED 0x000000FF
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#define CTRL_CLK_VIN_TYPE_DISABLED 0x00000000
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/*!
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* Mask of all GPC VIN IDs supported by RM
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*/
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#define CTRL_CLK_VIN_MASK_UNICAST_GPC (BIT(CTRL_CLK_VIN_ID_GPC0) | \
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BIT(CTRL_CLK_VIN_ID_GPC1) | \
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BIT(CTRL_CLK_VIN_ID_GPC2) | \
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BIT(CTRL_CLK_VIN_ID_GPC3) | \
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BIT(CTRL_CLK_VIN_ID_GPC4) | \
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BIT(CTRL_CLK_VIN_ID_GPC5))
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#define CTRL_CLK_LUT_NUM_ENTRIES 0x50
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#define CTRL_CLK_VIN_STEP_SIZE_UV (10000)
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#define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000)
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#define CTRL_CLK_FLL_TYPE_DISABLED 0
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#define CTRL_CLK_FLL_ID_SYS (0x00000000)
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#define CTRL_CLK_FLL_ID_LTC (0x00000001)
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#define CTRL_CLK_FLL_ID_XBAR (0x00000002)
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#define CTRL_CLK_FLL_ID_GPC0 (0x00000003)
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#define CTRL_CLK_FLL_ID_GPC1 (0x00000004)
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#define CTRL_CLK_FLL_ID_GPC2 (0x00000005)
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#define CTRL_CLK_FLL_ID_GPC3 (0x00000006)
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#define CTRL_CLK_FLL_ID_GPC4 (0x00000007)
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#define CTRL_CLK_FLL_ID_GPC5 (0x00000008)
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#define CTRL_CLK_FLL_ID_GPCS (0x00000009)
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#define CTRL_CLK_FLL_ID_UNDEFINED (0x000000FF)
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#define CTRL_CLK_FLL_MASK_UNDEFINED (0x00000000)
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/*!
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* Mask of all GPC FLL IDs supported by RM
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*/
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#define CTRL_CLK_FLL_MASK_UNICAST_GPC (BIT(CTRL_CLK_FLL_ID_GPC0) | \
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BIT(CTRL_CLK_FLL_ID_GPC1) | \
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BIT(CTRL_CLK_FLL_ID_GPC2) | \
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BIT(CTRL_CLK_FLL_ID_GPC3) | \
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BIT(CTRL_CLK_FLL_ID_GPC4) | \
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BIT(CTRL_CLK_FLL_ID_GPC5))
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/*!
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* Mask of all FLL IDs supported by RM
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*/
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#define CTRL_CLK_FLL_ID_ALL_MASK (BIT(CTRL_CLK_FLL_ID_SYS) | \
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BIT(CTRL_CLK_FLL_ID_LTC) | \
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BIT(CTRL_CLK_FLL_ID_XBAR) | \
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BIT(CTRL_CLK_FLL_ID_GPC0) | \
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BIT(CTRL_CLK_FLL_ID_GPC1) | \
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BIT(CTRL_CLK_FLL_ID_GPC2) | \
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BIT(CTRL_CLK_FLL_ID_GPC3) | \
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BIT(CTRL_CLK_FLL_ID_GPC4) | \
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BIT(CTRL_CLK_FLL_ID_GPC5) | \
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BIT(CTRL_CLK_FLL_ID_GPCS))
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#define CTRL_CLK_FLL_REGIME_ID_INVALID (0x00000000)
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#define CTRL_CLK_FLL_REGIME_ID_FFR (0x00000001)
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#define CTRL_CLK_FLL_REGIME_ID_FR (0x00000002)
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#endif
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