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54d2132b69
VOLT_RAIL_GET_VOLTAGE RPC is no longer available for turing auto profile. Instead volt_rail_get_status cmd will fetch the required voltage values. NVGPU-4326 Change-Id: I3270c259b92effd13b3183e52af689ea2dc35c37 Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2233106 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
82 lines
2.6 KiB
C
82 lines
2.6 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu.h>
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#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/boardobjgrp.h>
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#include <nvgpu/boardobjgrp_e32.h>
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#include <nvgpu/pmu/pmuif/ctrlvolt.h>
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#include <nvgpu/pmu/pmuif/ctrlperf.h>
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#include <nvgpu/string.h>
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#include <nvgpu/pmu/perf.h>
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#include <nvgpu/pmu/volt.h>
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#include <nvgpu/pmu/cmd.h>
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#include "volt_pmu.h"
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struct volt_rpc_pmucmdhandler_params {
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struct nv_pmu_volt_rpc *prpc_call;
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u32 success;
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};
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int nvgpu_volt_send_load_cmd_to_pmu(struct gk20a *g)
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{
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struct nvgpu_pmu *pmu = g->pmu;
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struct nv_pmu_rpc_struct_volt_load rpc;
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int status = 0;
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(void) memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_volt_load));
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PMU_RPC_EXECUTE(status, pmu, VOLT, LOAD, &rpc, 0);
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if (status != 0) {
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nvgpu_err(g, "Failed to execute RPC status=0x%x",
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status);
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}
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return status;
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}
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void nvgpu_pmu_volt_rpc_handler(struct gk20a *g, struct nv_pmu_rpc_header *rpc)
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{
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switch (rpc->function) {
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case NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD:
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nvgpu_pmu_dbg(g,
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"reply NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD");
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break;
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case NV_PMU_RPC_ID_VOLT_VOLT_SET_VOLTAGE:
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nvgpu_pmu_dbg(g,
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"reply NV_PMU_RPC_ID_VOLT_VOLT_SET_VOLTAGE");
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break;
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case NV_PMU_RPC_ID_VOLT_VOLT_RAIL_GET_VOLTAGE:
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nvgpu_pmu_dbg(g,
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"reply NV_PMU_RPC_ID_VOLT_VOLT_RAIL_GET_VOLTAGE");
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break;
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case NV_PMU_RPC_ID_VOLT_LOAD:
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nvgpu_pmu_dbg(g,
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"reply NV_PMU_RPC_ID_VOLT_LOAD");
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break;
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default:
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nvgpu_pmu_dbg(g, "invalid reply");
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break;
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}
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}
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