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55afe1ff4c
- Make the domain scheduler timeslice type nanoseconds to future proof the interface - Return -ENOSYS from ioctls if the nvs code is not initialized - Return the number of domains also when user supplied array is present - Use domain id instead of name for TSG binding - Improve documentation in the uapi headers - Verify that reserved fields are zeroed - Extend some internal logging - Release the sched mutex on alloc error - Add file mode checks in the nvs ioctls. The create and remove ioctls require writable file permissions, while the query does not; this allows filesystem based access control on domain management on the single dev node. Jira NVGPU-6788 Change-Id: I668eb5972a0ed1073e84a4ae30e3069bf0b59e16 Signed-off-by: Konsta Hölttä <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2639017 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
151 lines
4.0 KiB
C
151 lines
4.0 KiB
C
/*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _UAPI__LINUX_NVGPU_NVS_H
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#define _UAPI__LINUX_NVGPU_NVS_H
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#include "nvgpu-uapi-common.h"
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#define NVGPU_NVS_IOCTL_MAGIC 'N'
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/**
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* Domain parameters to pass to the kernel.
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*/
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struct nvgpu_nvs_ioctl_domain {
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/*
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* Human readable null-terminated name for this domain.
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*/
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char name[32];
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/*
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* Scheduling parameters: specify how long this domain should be scheduled
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* for and what the grace period the scheduler should give this domain when
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* preempting. A value of zero is treated as an infinite timeslice or an
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* infinite grace period, respectively.
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*/
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__u64 timeslice_ns;
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__u64 preempt_grace_ns;
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/*
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* Pick which subscheduler to use. These will be implemented by the kernel
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* as needed. There'll always be at least one, which is the host HW built in
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* round-robin scheduler.
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*/
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__u32 subscheduler;
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/*
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* GPU host hardware round-robin.
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*/
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#define NVGPU_SCHED_IOCTL_SUBSCHEDULER_HOST_HW_RR 0x0
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/*
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* Populated by the IOCTL when created: unique identifier. User space
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* must set this to 0.
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*/
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__u64 dom_id;
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/* Must be 0. */
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__u64 reserved1;
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/* Must be 0. */
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__u64 reserved2;
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};
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/**
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* NVGPU_NVS_IOCTL_CREATE_DOMAIN
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*
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* Create a domain - essentially a group of GPU contexts. Applications
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* can be bound into this domain on request for each TSG.
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*
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* The domain ID is returned in dom_id; this id is _not_ secure. The
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* nvsched device needs to have restricted permissions such that only a
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* single user, or group of users, has permissions to modify the
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* scheduler.
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*
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* It's fine to allow read-only access to the device node for other
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* users; this lets other users query scheduling information that may be
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* of interest to them.
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*/
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struct nvgpu_nvs_ioctl_create_domain {
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/*
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* In/out: domain parameters that userspace configures.
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*
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* The domain ID is returned here.
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*/
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struct nvgpu_nvs_ioctl_domain domain_params;
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/* Must be 0. */
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__u64 reserved1;
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};
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struct nvgpu_nvs_ioctl_remove_domain {
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/*
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* In: a domain_id to remove.
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*/
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__u64 dom_id;
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/* Must be 0. */
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__u64 reserved1;
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};
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/**
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* NVGPU_NVS_IOCTL_QUERY_DOMAINS
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*
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* Query the current list of domains in the scheduler. This is a two
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* part IOCTL.
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*
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* If domains is 0, then this IOCTL will populate nr with the number
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* of present domains.
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*
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* If domains is nonzero, then this IOCTL will treat domains as a pointer to an
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* array of nvgpu_nvs_ioctl_domain and will write up to nr domains into that
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* array. The nr field will be updated with the number of present domains,
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* which may be more than the number of entries written.
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*/
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struct nvgpu_nvs_ioctl_query_domains {
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/*
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* In/Out: If 0, leave untouched. If nonzero, then write up to nr
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* elements of nvgpu_nvs_ioctl_domain into where domains points to.
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*/
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__u64 domains;
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/*
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* - In: the capacity of the domains array if domais is not 0.
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* - Out: populate with the number of domains present.
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*/
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__u32 nr;
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/* Must be 0. */
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__u32 reserved0;
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/* Must be 0. */
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__u64 reserved1;
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};
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#define NVGPU_NVS_IOCTL_CREATE_DOMAIN \
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_IOWR(NVGPU_NVS_IOCTL_MAGIC, 1, \
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struct nvgpu_nvs_ioctl_create_domain)
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#define NVGPU_NVS_IOCTL_REMOVE_DOMAIN \
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_IOW(NVGPU_NVS_IOCTL_MAGIC, 2, \
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struct nvgpu_nvs_ioctl_remove_domain)
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#define NVGPU_NVS_IOCTL_QUERY_DOMAINS \
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_IOWR(NVGPU_NVS_IOCTL_MAGIC, 3, \
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struct nvgpu_nvs_ioctl_query_domains)
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#define NVGPU_NVS_IOCTL_LAST \
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_IOC_NR(NVGPU_NVS_IOCTL_QUERY_DOMAINS)
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#define NVGPU_NVS_IOCTL_MAX_ARG_SIZE \
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sizeof(struct nvgpu_nvs_ioctl_create_domain)
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#endif
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