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6299b00beb
This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt handling support for gm206 GPU family 5) Added generic mechanism to identify the CE engine pri_base address for gm206 (CE0, CE1 and CE2) 6) Removed hard coded engine_id logic and made generic way 7) Code cleanup for readability JIRA DNVGPU-26 Change-Id: I2c3846c40bcc8d10c2dfb225caa4105fc9123b65 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1155963 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
99 lines
2.8 KiB
C
99 lines
2.8 KiB
C
/*
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* GK20A Graphics Copy Engine (gr host)
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*
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* Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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/*TODO: remove uncecessary */
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/scatterlist.h>
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#include <trace/events/gk20a.h>
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#include <linux/dma-mapping.h>
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#include <linux/nvhost.h>
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#include "gk20a.h"
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#include "debug_gk20a.h"
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#include "semaphore_gk20a.h"
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#include "hw_ce2_gk20a.h"
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#include "hw_pbdma_gk20a.h"
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#include "hw_ccsr_gk20a.h"
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#include "hw_ram_gk20a.h"
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#include "hw_top_gk20a.h"
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#include "hw_mc_gk20a.h"
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#include "hw_gr_gk20a.h"
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static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr)
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{
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gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n");
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return ce2_intr_status_nonblockpipe_pending_f();
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}
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static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr)
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{
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gk20a_dbg(gpu_dbg_intr, "ce2 blocking pipe interrupt\n");
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return ce2_intr_status_blockpipe_pending_f();
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}
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static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr)
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{
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gk20a_dbg(gpu_dbg_intr, "ce2 launch error interrupt\n");
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return ce2_intr_status_launcherr_pending_f();
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}
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void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r());
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u32 clear_intr = 0;
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gk20a_dbg(gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr);
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/* clear blocking interrupts: they exibit broken behavior */
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if (ce2_intr & ce2_intr_status_blockpipe_pending_f())
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clear_intr |= ce2_blockpipe_isr(g, ce2_intr);
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if (ce2_intr & ce2_intr_status_launcherr_pending_f())
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clear_intr |= ce2_launcherr_isr(g, ce2_intr);
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gk20a_writel(g, ce2_intr_status_r(), clear_intr);
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return;
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}
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void gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r());
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gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr);
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if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) {
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gk20a_writel(g, ce2_intr_status_r(),
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ce2_nonblockpipe_isr(g, ce2_intr));
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/* wake threads waiting in this channel */
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gk20a_channel_semaphore_wakeup(g, true);
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}
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return;
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}
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void gk20a_init_ce2(struct gpu_ops *gops)
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{
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gops->ce2.isr_stall = gk20a_ce2_isr;
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gops->ce2.isr_nonstall = gk20a_ce2_nonstall_isr;
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}
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