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JIRA DNVGPU-45 Change-Id: I237ce81e31b036c05c82d46eea8694ffe1c2e3df Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1205849 (cherry picked from commit 9a4006f76b75a8ad525e7aa5ad1f609aaae49126) Reviewed-on: http://git-master/r/1227256 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
33 lines
879 B
C
33 lines
879 B
C
/*
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* general p state infrastructure
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*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ctrlperf_h_
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#define _ctrlperf_h_
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#include "ctrlvolt.h"
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struct ctrl_perf_volt_rail_list_item {
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u8 volt_domain;
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u32 voltage_uv;
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u32 voltage_min_noise_unaware_uv;
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};
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struct ctrl_perf_volt_rail_list {
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u8 num_rails;
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struct ctrl_perf_volt_rail_list_item
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rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
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};
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#endif
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