mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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57a75c3ba6
Add/update following prod settings: blcg ce slcg ce2 Change-Id: I10a62d980479ad23efd7033d29e269c4aac08834 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1030986 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
164 lines
4.5 KiB
C
164 lines
4.5 KiB
C
/*
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* GP10B Tegra HAL interface
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*
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* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/types.h>
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#include <linux/printk.h>
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#include <linux/types.h>
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#include "gk20a/gk20a.h"
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#include "gp10b/gr_gp10b.h"
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#include "gp10b/mc_gp10b.h"
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#include "gp10b/ltc_gp10b.h"
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#include "gp10b/mm_gp10b.h"
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#include "gp10b/ce2_gp10b.h"
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#include "gp10b/fb_gp10b.h"
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#include "gp10b/pmu_gp10b.h"
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#include "gp10b/gr_ctx_gp10b.h"
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#include "gp10b/fifo_gp10b.h"
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#include "gp10b/gp10b_gating_reglist.h"
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#include "gp10b/regops_gp10b.h"
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#include "gp10b/cde_gp10b.h"
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#include "gp10b/therm_gp10b.h"
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#include "gm20b/gr_gm20b.h"
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#include "gm20b/fifo_gm20b.h"
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#include "gm20b/pmu_gm20b.h"
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#include "gm20b/clk_gm20b.h"
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#include <linux/tegra-fuse.h>
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#define FUSE_OPT_PRIV_SEC_EN_0 0x264
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#define PRIV_SECURITY_ENABLED 0x01
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static struct gpu_ops gp10b_ops = {
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.clock_gating = {
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.slcg_bus_load_gating_prod =
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gp10b_slcg_bus_load_gating_prod,
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.slcg_ce2_load_gating_prod =
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gp10b_slcg_ce2_load_gating_prod,
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.slcg_chiplet_load_gating_prod =
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gp10b_slcg_chiplet_load_gating_prod,
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.slcg_ctxsw_firmware_load_gating_prod =
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gp10b_slcg_ctxsw_firmware_load_gating_prod,
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.slcg_fb_load_gating_prod =
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gp10b_slcg_fb_load_gating_prod,
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.slcg_fifo_load_gating_prod =
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gp10b_slcg_fifo_load_gating_prod,
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.slcg_gr_load_gating_prod =
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gr_gp10b_slcg_gr_load_gating_prod,
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.slcg_ltc_load_gating_prod =
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ltc_gp10b_slcg_ltc_load_gating_prod,
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.slcg_perf_load_gating_prod =
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gp10b_slcg_perf_load_gating_prod,
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.slcg_priring_load_gating_prod =
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gp10b_slcg_priring_load_gating_prod,
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.slcg_pmu_load_gating_prod =
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gp10b_slcg_pmu_load_gating_prod,
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.slcg_therm_load_gating_prod =
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gp10b_slcg_therm_load_gating_prod,
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.slcg_xbar_load_gating_prod =
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gp10b_slcg_xbar_load_gating_prod,
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.blcg_bus_load_gating_prod =
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gp10b_blcg_bus_load_gating_prod,
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.blcg_ce_load_gating_prod =
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gp10b_blcg_ce_load_gating_prod,
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.blcg_ctxsw_firmware_load_gating_prod =
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gp10b_blcg_ctxsw_firmware_load_gating_prod,
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.blcg_fb_load_gating_prod =
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gp10b_blcg_fb_load_gating_prod,
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.blcg_fifo_load_gating_prod =
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gp10b_blcg_fifo_load_gating_prod,
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.blcg_gr_load_gating_prod =
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gp10b_blcg_gr_load_gating_prod,
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.blcg_ltc_load_gating_prod =
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gp10b_blcg_ltc_load_gating_prod,
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.blcg_pwr_csb_load_gating_prod =
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gp10b_blcg_pwr_csb_load_gating_prod,
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.blcg_pmu_load_gating_prod =
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gp10b_blcg_pmu_load_gating_prod,
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.blcg_xbar_load_gating_prod =
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gp10b_blcg_xbar_load_gating_prod,
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.pg_gr_load_gating_prod =
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gr_gp10b_pg_gr_load_gating_prod,
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}
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};
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int gp10b_init_hal(struct gk20a *g)
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{
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struct gpu_ops *gops = &g->ops;
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struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
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*gops = gp10b_ops;
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#ifdef CONFIG_TEGRA_ACR
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if (tegra_platform_is_linsim()) {
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gops->privsecurity = 0;
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gops->securegpccs = 0;
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} else {
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if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) &
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PRIV_SECURITY_ENABLED) {
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gops->privsecurity = 1;
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gops->securegpccs =1;
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} else {
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gk20a_dbg_info("priv security is disabled in HW");
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gops->privsecurity = 0;
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gops->securegpccs = 0;
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}
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}
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#else
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if (tegra_platform_is_linsim()) {
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gk20a_dbg_info("running ASIM with PRIV security disabled");
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gops->privsecurity = 0;
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gops->securegpccs = 0;
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} else {
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if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) &
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PRIV_SECURITY_ENABLED) {
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gk20a_dbg_info("priv security is not supported but enabled");
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gops->privsecurity = 1;
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gops->securegpccs =1;
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return -EPERM;
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} else {
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gops->privsecurity = 0;
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gops->securegpccs = 0;
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}
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}
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#endif
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gp10b_init_mc(gops);
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gp10b_init_gr(gops);
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gp10b_init_ltc(gops);
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gp10b_init_fb(gops);
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gp10b_init_fifo(gops);
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gp10b_init_ce2(gops);
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gp10b_init_gr_ctx(gops);
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gp10b_init_mm(gops);
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gp10b_init_pmu_ops(gops);
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gk20a_init_debug_ops(gops);
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gp10b_init_regops(gops);
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gp10b_init_cde_ops(gops);
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gp10b_init_therm_ops(gops);
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gops->name = "gp10b";
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c->twod_class = FERMI_TWOD_A;
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c->threed_class = PASCAL_A;
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c->compute_class = PASCAL_COMPUTE_A;
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c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A;
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c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
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c->dma_copy_class = PASCAL_DMA_COPY_A;
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return 0;
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}
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