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57be9a09fd
channel.c calling nvgpu_gr_flush_channel_tlb() creating circular dependency between gr and fifo. Avoid this by moving channel tlb related data to struct nvgpu_gr_intr in gr_intr_priv.h and initialized this data in gr_intr.c. Created following new gr intr hal and called this new hal from channel.c void (*flush_channel_tlb)(struct gk20a *g); JIRA NVGPU-3214 Change-Id: I2d259bf52db967273030680f50065af94a17f417 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2109274 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
81 lines
2.2 KiB
C
81 lines
2.2 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_PRIV_H
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#define NVGPU_GR_PRIV_H
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#include <nvgpu/types.h>
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#include <nvgpu/cond.h>
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struct nvgpu_gr_ctx_desc;
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struct nvgpu_gr_global_ctx_buffer_desc;
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struct nvgpu_gr_obj_ctx_golden_image;
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struct nvgpu_gr_config;
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struct nvgpu_gr_zbc;
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struct nvgpu_gr_hwpm_map;
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struct nvgpu_gr_zcull;
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struct gk20a_cs_snapshot;
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struct nvgpu_gr {
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struct gk20a *g;
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struct nvgpu_cond init_wq;
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bool initialized;
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u32 num_fbps;
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u32 max_fbps_count;
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struct nvgpu_gr_global_ctx_buffer_desc *global_ctx_buffer;
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struct nvgpu_gr_obj_ctx_golden_image *golden_image;
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struct nvgpu_gr_ctx_desc *gr_ctx_desc;
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struct nvgpu_gr_config *config;
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struct nvgpu_gr_hwpm_map *hwpm_map;
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struct nvgpu_gr_zcull *zcull;
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struct nvgpu_gr_zbc *zbc;
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struct nvgpu_gr_falcon *falcon;
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struct nvgpu_gr_intr *intr;
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void (*remove_support)(struct gk20a *g);
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bool sw_ready;
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u32 fecs_feature_override_ecc_val;
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u32 cilp_preempt_pending_chid;
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u32 fbp_en_mask;
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u32 *fbp_rop_l2_en_mask;
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struct nvgpu_mutex ctxsw_disable_mutex;
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int ctxsw_disable_count;
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};
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#endif /* NVGPU_GR_PRIV_H */
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