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57f03e3a200074d0c6b977df0c76db86adc6b877
linux-nvgpu/drivers/gpu/nvgpu/common/ltc
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Deepak Nibade 8ef20036c7 gpu: nvgpu: tu104: disable PLC compression 
PLC compression on Turing has a h/w bug, hence keep it disabled

Bug 2427473
Jira NVGPU-1322

Change-Id: I00a9cb652d4d854d146d865a8f61949c7f846d78
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969438
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-12-11 12:34:15 -08:00
..
ltc_gm20b.c
gpu: nvgpu: common: fix MISRA Rule 10.4 Violations
2018-12-11 10:26:16 -08:00
ltc_gm20b.h
gpu: nvgpu: Split L2 interrupt handling to MC and L2
2018-10-24 17:00:01 -07:00
ltc_gp10b.c
gpu: nvgpu: common: fix MISRA Rule 10.4 Violations
2018-12-11 10:26:16 -08:00
ltc_gp10b.h
gpu: nvgpu: Split L2 interrupt handling to MC and L2
2018-10-24 17:00:01 -07:00
ltc_gv11b.c
gpu: nvgpu: common: fix MISRA Rule 10.4 Violations
2018-12-11 10:26:16 -08:00
ltc_gv11b.h
gpu: nvgpu: Split L2 interrupt handling to MC and L2
2018-10-24 17:00:01 -07:00
ltc_tu104.c
gpu: nvgpu: tu104: disable PLC compression
2018-12-11 12:34:15 -08:00
ltc_tu104.h
gpu: nvgpu: Split L2 interrupt handling to MC and L2
2018-10-24 17:00:01 -07:00
ltc.c
nvgpu: common: MISRA 10.1 boolean fixes
2018-10-29 14:44:38 -07:00