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git://nv-tegra.nvidia.com/linux-nvgpu.git
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57f3968cb9
Address following issues uncovered during inspection: 1. Remove the doxygen comment from nvgpu_wait_for_deferred_interrupts definition. 2. Use NVGPU_MC_INTR_STALLING instead of hardcoding the index. 3. Define doxygen groups NVGPU_MC_UNIT_ENUMS, NVGPU_MC_INTR_TYPE_DEFINES, NVGPU_MC_INTR_UNIT_DEFINES and NVGPU_MC_INTR_ENABLE_DEFINES. 4. Update the doxygen comments. 5. Fix the cleanup, typo in the description of the test test_wait_for_deferred_interrupts. JIRA NVGPU-4795 Change-Id: Ifc6756832aabf9dd42ee174eb1373495e6d38c86 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287627 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
125 lines
3.6 KiB
C
125 lines
3.6 KiB
C
/*
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* GK20A Master Control
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*
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* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/mc.h>
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#include <nvgpu/gk20a.h>
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void nvgpu_wait_for_deferred_interrupts(struct gk20a *g)
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{
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/* wait until all stalling irqs are handled */
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NVGPU_COND_WAIT(&g->mc.sw_irq_stall_last_handled_cond,
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nvgpu_atomic_read(&g->mc.sw_irq_stall_pending) == 0,
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0U);
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/* wait until all non-stalling irqs are handled */
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NVGPU_COND_WAIT(&g->mc.sw_irq_nonstall_last_handled_cond,
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nvgpu_atomic_read(&g->mc.sw_irq_nonstall_pending) == 0,
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0U);
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}
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void nvgpu_mc_intr_mask(struct gk20a *g)
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{
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unsigned long flags = 0;
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if (g->ops.mc.intr_mask != NULL) {
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nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
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g->ops.mc.intr_mask(g);
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nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
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}
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}
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#ifdef CONFIG_NVGPU_NON_FUSA
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void nvgpu_mc_log_pending_intrs(struct gk20a *g)
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{
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if (g->ops.mc.log_pending_intrs != NULL) {
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g->ops.mc.log_pending_intrs(g);
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}
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}
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void nvgpu_mc_intr_enable(struct gk20a *g)
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{
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unsigned long flags = 0;
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if (g->ops.mc.intr_enable != NULL) {
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nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
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g->ops.mc.intr_enable(g);
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nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
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}
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}
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#endif
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void nvgpu_mc_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable)
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{
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unsigned long flags = 0;
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nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
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g->ops.mc.intr_stall_unit_config(g, unit, enable);
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nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
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}
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void nvgpu_mc_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable)
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{
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unsigned long flags = 0;
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nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
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g->ops.mc.intr_nonstall_unit_config(g, unit, enable);
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nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
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}
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void nvgpu_mc_intr_stall_pause(struct gk20a *g)
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{
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unsigned long flags = 0;
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nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
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g->ops.mc.intr_stall_pause(g);
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nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
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}
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void nvgpu_mc_intr_stall_resume(struct gk20a *g)
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{
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unsigned long flags = 0;
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nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
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g->ops.mc.intr_stall_resume(g);
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nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
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}
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void nvgpu_mc_intr_nonstall_pause(struct gk20a *g)
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{
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unsigned long flags = 0;
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nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
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g->ops.mc.intr_nonstall_pause(g);
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nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
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}
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void nvgpu_mc_intr_nonstall_resume(struct gk20a *g)
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{
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unsigned long flags = 0;
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nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
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g->ops.mc.intr_nonstall_resume(g);
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nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
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}
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