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ef524ee0d1
-Currently PG task is created for both iGPU & dGPU as part PMU init sequence path, but task is not required for dGPU or can be skipped if ELPG is not supported on iGPU, made changes to create PG task only if supported else skip it, and made some functions to private as these are required by PG UNIT only. -PG instance is allocated & set to default properties as needed if support is enabled else skip it. -Made changes in dependent files as required to reflect above changes JIRA NVGPU-1972 Change-Id: I4efb7f1814a9ad48770acea2173e66f0a4c8a9c1 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2094840 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
114 lines
3.2 KiB
C
114 lines
3.2 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/pmu/fw.h>
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bool nvgpu_find_hex_in_string(char *strings, struct gk20a *g, u32 *hex_pos)
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{
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u32 i = 0, j = (u32)strlen(strings);
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for (; i < j; i++) {
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if (strings[i] == '%') {
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if (strings[i + 1U] == 'x' || strings[i + 1U] == 'X') {
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*hex_pos = i;
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return true;
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}
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}
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}
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*hex_pos = U32_MAX;
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return false;
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}
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static void print_pmu_trace(struct nvgpu_pmu *pmu)
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{
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struct gk20a *g = pmu->g;
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u32 i = 0, j = 0, k, l, m;
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int count;
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char part_str[40], buf[0x40];
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void *tracebuffer;
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char *trace;
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u32 *trace1;
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/* allocate system memory to copy pmu trace buffer */
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tracebuffer = nvgpu_kzalloc(g, GK20A_PMU_TRACE_BUFSIZE);
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if (tracebuffer == NULL) {
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return;
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}
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/* read pmu traces into system memory buffer */
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nvgpu_mem_rd_n(g, &pmu->trace_buf, 0, tracebuffer,
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GK20A_PMU_TRACE_BUFSIZE);
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trace = (char *)tracebuffer;
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trace1 = (u32 *)tracebuffer;
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nvgpu_err(g, "dump PMU trace buffer");
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for (i = 0U; i < GK20A_PMU_TRACE_BUFSIZE; i += 0x40U) {
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for (j = 0U; j < 0x40U; j++) {
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if (trace1[(i / 4U) + j] != 0U) {
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break;
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}
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}
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if (j == 0x40U) {
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break;
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}
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count = scnprintf(buf, 0x40, "Index %x: ", trace1[(i / 4U)]);
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l = 0;
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m = 0;
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while (nvgpu_find_hex_in_string((trace+i+20+m), g, &k)) {
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if (k >= 40U) {
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break;
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}
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(void) strncpy(part_str, (trace+i+20+m), k);
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part_str[k] = '\0';
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count += scnprintf((buf + count), 0x40, "%s0x%x",
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part_str, trace1[(i / 4U) + 1U + l]);
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l++;
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m += k + 2U;
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}
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(void) scnprintf((buf + count), 0x40, "%s", (trace+i+20+m));
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nvgpu_err(g, "%s", buf);
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}
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nvgpu_kfree(g, tracebuffer);
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}
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void nvgpu_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu)
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{
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struct gk20a *g = pmu->g;
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nvgpu_falcon_dump_stats(&pmu->flcn);
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g->ops.pmu.pmu_dump_falcon_stats(pmu);
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/* Print PMU F/W debug prints */
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print_pmu_trace(pmu);
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nvgpu_err(g, "pmu state: %d", nvgpu_pmu_get_fw_state(g, pmu));
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nvgpu_err(g, "elpg state: %d", pmu->pg->elpg_stat);
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/* PMU may crash due to FECS crash. Dump FECS status */
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g->ops.gr.falcon.dump_stats(g);
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}
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