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c0a0b6419d
In gr_gv100_get_active_fpba_mask(), we directly access top_* register from hw_top_gv100.h h/w header to read FBPA count. Add a new HAL in TOP unit to return max FBPA count g->ops.top.get_max_fbpas_count() Use this HAL in gr_gv100.c to get FBPA count and remove direct access of top_* register, and also remove hw_top_gv100.h header include Jira NVGPU-2895 Change-Id: Idfba553b24d7d6abf124a84b1490987e8cbf1985 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2069470 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
75 lines
2.2 KiB
C
75 lines
2.2 KiB
C
/*
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* GV100 TOP UNIT
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "top_gv100.h"
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#include <nvgpu/hw/gv100/hw_top_gv100.h>
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u32 gv100_top_get_nvhsclk_ctrl_e_clk_nvl(struct gk20a *g)
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{
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u32 reg;
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reg = nvgpu_readl(g, top_nvhsclk_ctrl_r());
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return top_nvhsclk_ctrl_e_clk_nvl_v(reg);
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}
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void gv100_top_set_nvhsclk_ctrl_e_clk_nvl(struct gk20a *g, u32 val)
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{
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u32 reg;
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reg = nvgpu_readl(g, top_nvhsclk_ctrl_r());
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reg = set_field(reg, top_nvhsclk_ctrl_e_clk_nvl_m(),
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top_nvhsclk_ctrl_e_clk_nvl_f(val));
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nvgpu_writel(g, top_nvhsclk_ctrl_r(), reg);
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}
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u32 gv100_top_get_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g)
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{
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u32 reg;
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reg = nvgpu_readl(g, top_nvhsclk_ctrl_r());
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return top_nvhsclk_ctrl_swap_clk_nvl_v(reg);
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}
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void gv100_top_set_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g, u32 val)
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{
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u32 reg;
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reg = nvgpu_readl(g, top_nvhsclk_ctrl_r());
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reg = set_field(reg, top_nvhsclk_ctrl_swap_clk_nvl_m(),
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top_nvhsclk_ctrl_swap_clk_nvl_f(val));
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nvgpu_writel(g, top_nvhsclk_ctrl_r(), reg);
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}
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u32 gv100_top_get_max_fbpas_count(struct gk20a *g)
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{
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u32 tmp;
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tmp = nvgpu_readl(g, top_num_fbpas_r());
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return top_num_fbpas_value_v(tmp);
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}
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