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Currently in case of any fecs error, we only dump fecs cxtsw fw related registers, mailboxes and trace registers. With this change, we want to ensure we dump gpccs register space as well. This will help in debugging ctxsw related failures JIRA NVGPU-9560 Bug 3907163 Change-Id: I61e25883da4455ea1412ca70c5fc3377d9a786a3 Signed-off-by: Kishan <kpalankar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2850402 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
58 lines
2.0 KiB
C
58 lines
2.0 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu.h>
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#include <nvgpu/log.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
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void nvgpu_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu)
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{
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struct gk20a *g = pmu->g;
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/* Print PG stats */
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nvgpu_err(g, "Print PG stats");
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nvgpu_flcn_print_dmem(pmu->flcn,
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pmu->stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_GRAPHICS],
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sizeof(struct pmu_pg_stats_v2));
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g->ops.pmu.pmu_dump_elpg_stats(pmu);
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}
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void nvgpu_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu)
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{
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struct gk20a *g = pmu->g;
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nvgpu_flcn_dump_stats(pmu->flcn);
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g->ops.pmu.pmu_dump_falcon_stats(pmu);
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nvgpu_err(g, "pmu state: %d", pmu->pmu_state);
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nvgpu_err(g, "elpg state: %d", pmu->elpg_stat);
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/* PMU may crash due to FECS crash. Dump FECS and GPCCS status */
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gk20a_fecs_dump_falcon_stats(g);
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gk20a_gpccs_dump_falcon_stats(g);
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}
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