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83103cdcca
nvgpu_channel_sync_set_min_eq_max is not used as part of the safety build and hence is moved out. channel_sync_syncpt_set_min_eq_max is also moved out as a part of the above function. Also add a branch coverage for the case when g->disable_syncpoints is set to true. Jira NVGPU-913 Change-Id: I2512d01e105551732aad63b2800bb4cb6d913cb2 Signed-off-by: ddutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2263003 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
72 lines
2.4 KiB
C
72 lines
2.4 KiB
C
/*
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*
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* Nvgpu Channel Synchronization Abstraction
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CHANNEL_SYNC_PRIV_H
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#define NVGPU_CHANNEL_SYNC_PRIV_H
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#include <nvgpu/atomic.h>
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#include <nvgpu/types.h>
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struct priv_cmd_entry;
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struct nvgpu_fence_type;
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/*
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* This struct is private and should not be used directly. Users should
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* instead use the public APIs starting with nvgpu_channel_sync_*
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*/
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struct nvgpu_channel_sync {
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nvgpu_atomic_t refcount;
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#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
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int (*wait_fence_raw)(struct nvgpu_channel_sync *s, u32 id, u32 thresh,
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struct priv_cmd_entry *entry);
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int (*wait_fence_fd)(struct nvgpu_channel_sync *s, int fd,
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struct priv_cmd_entry *entry, u32 max_wait_cmds);
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int (*incr)(struct nvgpu_channel_sync *s,
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struct priv_cmd_entry *entry,
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struct nvgpu_fence_type *fence,
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bool need_sync_fence,
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bool register_irq);
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int (*incr_user)(struct nvgpu_channel_sync *s,
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int wait_fence_fd,
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struct priv_cmd_entry *entry,
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struct nvgpu_fence_type *fence,
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bool wfi,
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bool need_sync_fence,
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bool register_irq);
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void (*set_min_eq_max)(struct nvgpu_channel_sync *s);
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#endif
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void (*set_safe_state)(struct nvgpu_channel_sync *s);
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void (*destroy)(struct nvgpu_channel_sync *s);
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};
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#endif /* NVGPU_CHANNEL_SYNC_PRIV_H */
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