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5d30a5cda3
-Created struct nvgpu_acr to hold acr module related member within single struct which are currently spread across multiple structs like nvgpu_pmu, pmu_ops & gk20a. -Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members -Created struct hs_acr to hold ACR ucode specific members like bootloader data using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run. -Created acr ops under struct nvgpu_acr to perform ACR specific operation, currently ACR ops were part PMU which caused to have always dependence on PMU even though ACR was not executing on PMU. -Added acr_remove_support ops which will be called as part of gk20a_remove_support() method, earlier acr cleanup was part of pmu remove_support method. -Created define for ACR types, -Ops acr_sw_init() function helps to set ACR properties statically for chip currently in execution & assign ops to point to needed functions as per chip. -Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr function to alloc blob space. -Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde based on interfaces used to bootstrap ACR ucode. -Created function gm20b_bootstrap_hs_acr() function which is now common HAL for all chips to bootstrap ACR, earlier had 3 different function for gm20b/gp10b, gv11b & for all dgpu based on interface needed. -Removed duplicate code for falcon engine wherever common falcon code can be used. -Removed ACR code dependent on PMU & made changes to use from nvgpu_acr. JIRA NVGPU-1148 Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813231 GVS: Gerrit_Virtual_Submit Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
69 lines
2.9 KiB
C
69 lines
2.9 KiB
C
/*
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* GM20B ACR
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*
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* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GM20B_ACR_GM20B_H
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#define NVGPU_GM20B_ACR_GM20B_H
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#define GM20B_PMU_UCODE_IMAGE "gpmu_ucode_image.bin"
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#define GM20B_PMU_UCODE_DESC "gpmu_ucode_desc.bin"
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#define GM20B_HSBIN_PMU_UCODE_IMAGE "acr_ucode.bin"
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#define GM20B_HSBIN_PMU_BL_UCODE_IMAGE "pmu_bl.bin"
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#define GM20B_PMU_UCODE_SIG "pmu_sig.bin"
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#define GM20B_FECS_UCODE_SIG "fecs_sig.bin"
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#define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin"
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bool gm20b_is_pmu_supported(struct gk20a *g);
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int prepare_ucode_blob(struct gk20a *g);
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bool gm20b_is_lazy_bootstrap(u32 falcon_id);
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bool gm20b_is_priv_load(u32 falcon_id);
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int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
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void *lsfm, u32 *p_bl_gen_desc_size);
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int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g,
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void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
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void gm20b_update_lspmu_cmdline_args(struct gk20a *g);
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void gm20b_setup_apertures(struct gk20a *g);
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int gm20b_pmu_setup_sw(struct gk20a *g);
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int gm20b_init_nspmu_setup_hw1(struct gk20a *g);
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int acr_ucode_patch_sig(struct gk20a *g,
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unsigned int *p_img,
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unsigned int *p_prod_sig,
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unsigned int *p_dbg_sig,
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unsigned int *p_patch_loc,
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unsigned int *p_patch_ind);
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int gm20b_alloc_blob_space(struct gk20a *g,
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size_t size, struct nvgpu_mem *mem);
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void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
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int gm20b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
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struct nvgpu_acr *acr, struct hs_acr *acr_desc, bool is_recovery);
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int gm20b_acr_fill_bl_dmem_desc(struct gk20a *g,
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struct nvgpu_acr *acr, struct hs_acr *acr_desc,
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u32 *acr_ucode_header);
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int gm20b_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr,
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struct hs_acr *acr_desc);
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void gm20b_remove_acr_support(struct nvgpu_acr *acr);
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void nvgpu_gm20b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
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#endif /*NVGPU_GM20B_ACR_GM20B_H*/
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