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git://nv-tegra.nvidia.com/linux-nvgpu.git
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5d30a5cda3
-Created struct nvgpu_acr to hold acr module related member within single struct which are currently spread across multiple structs like nvgpu_pmu, pmu_ops & gk20a. -Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members -Created struct hs_acr to hold ACR ucode specific members like bootloader data using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run. -Created acr ops under struct nvgpu_acr to perform ACR specific operation, currently ACR ops were part PMU which caused to have always dependence on PMU even though ACR was not executing on PMU. -Added acr_remove_support ops which will be called as part of gk20a_remove_support() method, earlier acr cleanup was part of pmu remove_support method. -Created define for ACR types, -Ops acr_sw_init() function helps to set ACR properties statically for chip currently in execution & assign ops to point to needed functions as per chip. -Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr function to alloc blob space. -Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde based on interfaces used to bootstrap ACR ucode. -Created function gm20b_bootstrap_hs_acr() function which is now common HAL for all chips to bootstrap ACR, earlier had 3 different function for gm20b/gp10b, gv11b & for all dgpu based on interface needed. -Removed duplicate code for falcon engine wherever common falcon code can be used. -Removed ACR code dependent on PMU & made changes to use from nvgpu_acr. JIRA NVGPU-1148 Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813231 GVS: Gerrit_Virtual_Submit Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
118 lines
3.8 KiB
C
118 lines
3.8 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu.h>
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#include <nvgpu/falcon.h>
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#include <nvgpu/mm.h>
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#include <nvgpu/io.h>
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#include <nvgpu/timers.h>
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#include "gk20a/gk20a.h"
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#include "sec2_gp106.h"
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#include <nvgpu/hw/gp106/hw_pwr_gp106.h>
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#include <nvgpu/hw/gp106/hw_psec_gp106.h>
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int gp106_sec2_reset(struct gk20a *g)
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{
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nvgpu_log_fn(g, " ");
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gk20a_writel(g, psec_falcon_engine_r(),
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pwr_falcon_engine_reset_true_f());
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nvgpu_udelay(10);
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gk20a_writel(g, psec_falcon_engine_r(),
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pwr_falcon_engine_reset_false_f());
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nvgpu_log_fn(g, "done");
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return 0;
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}
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static int sec2_flcn_bl_bootstrap(struct gk20a *g,
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struct nvgpu_falcon_bl_info *bl_info)
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{
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struct mm_gk20a *mm = &g->mm;
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u32 data = 0U;
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int err = 0U;
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nvgpu_log_fn(g, " ");
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/* SEC2 Config */
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gk20a_writel(g, psec_falcon_itfen_r(),
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gk20a_readl(g, psec_falcon_itfen_r()) |
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psec_falcon_itfen_ctxen_enable_f());
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gk20a_writel(g, psec_falcon_nxtctx_r(),
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pwr_pmu_new_instblk_ptr_f(
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nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12U) |
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pwr_pmu_new_instblk_valid_f(1U) |
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nvgpu_aperture_mask(g, &mm->pmu.inst_block,
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pwr_pmu_new_instblk_target_sys_ncoh_f(),
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pwr_pmu_new_instblk_target_sys_coh_f(),
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pwr_pmu_new_instblk_target_fb_f()));
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data = gk20a_readl(g, psec_falcon_debug1_r());
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data |= psec_falcon_debug1_ctxsw_mode_m();
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gk20a_writel(g, psec_falcon_debug1_r(), data);
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data = gk20a_readl(g, psec_falcon_engctl_r());
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data |= (1U << 3U);
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gk20a_writel(g, psec_falcon_engctl_r(), data);
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err = nvgpu_flcn_bl_bootstrap(&g->sec2_flcn, bl_info);
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return err;
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}
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int gp106_sec2_setup_hw_and_bl_bootstrap(struct gk20a *g,
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struct hs_acr *acr_desc,
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struct nvgpu_falcon_bl_info *bl_info)
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{
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u32 data = 0U;
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nvgpu_log_fn(g, " ");
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nvgpu_flcn_reset(&g->sec2_flcn);
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data = gk20a_readl(g, psec_fbif_ctl_r());
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data |= psec_fbif_ctl_allow_phys_no_ctx_allow_f();
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gk20a_writel(g, psec_fbif_ctl_r(), data);
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/* setup apertures - virtual */
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gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
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psec_fbif_transcfg_mem_type_physical_f() |
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psec_fbif_transcfg_target_local_fb_f());
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gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
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psec_fbif_transcfg_mem_type_virtual_f());
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/* setup apertures - physical */
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gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
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psec_fbif_transcfg_mem_type_physical_f() |
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psec_fbif_transcfg_target_local_fb_f());
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gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
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psec_fbif_transcfg_mem_type_physical_f() |
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psec_fbif_transcfg_target_coherent_sysmem_f());
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gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
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psec_fbif_transcfg_mem_type_physical_f() |
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psec_fbif_transcfg_target_noncoherent_sysmem_f());
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return sec2_flcn_bl_bootstrap(g, bl_info);
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}
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