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c33d9767da
ACR WPR/blob-alloc functions are called from different parts of ACR UNIT like bootstrap, blob-construct & chip specific ACR sw init functions, these functions are part of acr.c which adds circular dependency between acr.c & other files, so, moved to respective new fiels based on its operation & also cleaned up header dependency. JIRA NVGPU-2907 Change-Id: I78d1eab59757029017d6ca62cbfc227a7a8240e4 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2081632 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
117 lines
3.7 KiB
C
117 lines
3.7 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef ACR_FALCON_BL_H
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#define ACR_FALCON_BL_H
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#include <nvgpu/flcnif_cmn.h>
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/* Falcon BL interfaces */
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/*
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* Structure used by the boot-loader to load the rest of the code. This has
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* to be filled by NVGPU and copied into DMEM at offset provided in the
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* hsflcn_bl_desc.bl_desc_dmem_load_off.
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*/
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struct flcn_bl_dmem_desc {
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u32 reserved[4]; /*Should be the first element..*/
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u32 signature[4]; /*Should be the first element..*/
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u32 ctx_dma;
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u32 code_dma_base;
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u32 non_sec_code_off;
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u32 non_sec_code_size;
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u32 sec_code_off;
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u32 sec_code_size;
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u32 code_entry_point;
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u32 data_dma_base;
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u32 data_size;
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u32 code_dma_base1;
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u32 data_dma_base1;
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};
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struct flcn_bl_dmem_desc_v1 {
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u32 reserved[4]; /*Should be the first element..*/
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u32 signature[4]; /*Should be the first element..*/
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u32 ctx_dma;
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struct falc_u64 code_dma_base;
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u32 non_sec_code_off;
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u32 non_sec_code_size;
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u32 sec_code_off;
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u32 sec_code_size;
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u32 code_entry_point;
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struct falc_u64 data_dma_base;
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u32 data_size;
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u32 argc;
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u32 argv;
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};
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/* HS Falcon BL interfaces */
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/*
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* The header used by NVGPU to figure out code and data sections of bootloader
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*
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* bl_code_off - Offset of code section in the image
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* bl_code_size - Size of code section in the image
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* bl_data_off - Offset of data section in the image
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* bl_data_size - Size of data section in the image
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*/
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struct flcn_bl_img_hdr {
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u32 bl_code_off;
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u32 bl_code_size;
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u32 bl_data_off;
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u32 bl_data_size;
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};
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/*
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* The descriptor used by NVGPU to figure out the requirements of bootloader
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*
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* bl_start_tag - Starting tag of bootloader
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* bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc
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* to be loaded
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* bl_img_hdr - Description of the image
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*/
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struct hsflcn_bl_desc {
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u32 bl_start_tag;
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u32 bl_desc_dmem_load_off;
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struct flcn_bl_img_hdr bl_img_hdr;
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};
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/*
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* Legacy structure used by the current PMU bootloader.
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*/
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struct loader_config {
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u32 dma_idx;
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u32 code_dma_base; /* upper 32-bits of 40-bit dma address */
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u32 code_size_total;
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u32 code_size_to_load;
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u32 code_entry_point;
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u32 data_dma_base; /* upper 32-bits of 40-bit dma address */
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u32 data_size; /* initialized data of the application */
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u32 overlay_dma_base; /* upper 32-bits of the 40-bit dma address */
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u32 argc;
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u32 argv;
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u16 code_dma_base1; /* upper 7 bits of 47-bit dma address */
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u16 data_dma_base1; /* upper 7 bits of 47-bit dma address */
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u16 overlay_dma_base1; /* upper 7 bits of the 47-bit dma address */
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};
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#endif /* ACR_FALCON_BL_H */
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