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170d7464d6
Move fifo_gk20a struct to fifo.h Move fifo_gk20a.[ch] to hal/fifo Add missing includes for fifo subunits. JIRA NVGPU-2012 Change-Id: I8bf5402bd5a9f8ff9f6a818cee553b57e117f3bc Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2109012 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
84 lines
2.7 KiB
C
84 lines
2.7 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/debug.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/engine_status.h>
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#include <nvgpu/hw/gv100/hw_fifo_gv100.h>
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#include "engine_status_gm20b.h"
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#include "engine_status_gv100.h"
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void gv100_read_engine_status_info(struct gk20a *g, u32 engine_id,
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struct nvgpu_engine_status_info *status)
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{
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u32 engine_reg_data;
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gm20b_read_engine_status_info(g, engine_id, status);
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engine_reg_data = status->reg_data;
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/* populate the engine reload status */
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status->in_reload_status =
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fifo_engine_status_eng_reload_v(engine_reg_data) != 0U;
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return;
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}
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void gv100_dump_engine_status(struct gk20a *g, struct gk20a_debug_output *o)
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{
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u32 i, host_num_engines;
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struct nvgpu_engine_status_info engine_status;
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host_num_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
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for (i = 0; i < host_num_engines; i++) {
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g->ops.engine_status.read_engine_status_info(g, i, &engine_status);
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gk20a_debug_output(o, "%s eng %d: ", g->name, i);
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gk20a_debug_output(o,
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"id: %d (%s), next_id: %d (%s), ctx status: %s ",
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engine_status.ctx_id,
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nvgpu_engine_status_is_ctx_type_tsg(
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&engine_status) ?
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"tsg" : "channel",
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engine_status.ctx_next_id,
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nvgpu_engine_status_is_next_ctx_type_tsg(
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&engine_status) ?
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"tsg" : "channel",
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nvgpu_fifo_decode_pbdma_ch_eng_status(
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engine_status.ctxsw_state));
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if (engine_status.in_reload_status) {
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gk20a_debug_output(o, "ctx_reload ");
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}
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if (engine_status.is_faulted) {
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gk20a_debug_output(o, "faulted ");
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}
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if (engine_status.is_busy) {
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gk20a_debug_output(o, "busy ");
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}
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gk20a_debug_output(o, "\n");
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}
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gk20a_debug_output(o, "\n");
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}
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