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9346b104d4
Created sub-unit for ltc interrupt handling. Following 2-hals are moved from ltc to ltc intr unit: void (*isr)(struct gk20a *g, u32 ltc); void (*en_illegal_compstat)(struct gk20a *g, bool enable) Added new hal in ltc intr sub-unit for configuring ltc interrupts: void (*configure)(struct gk20a *g); Moved ltc interrupt related code from ltc to ltc intr unit. Chip ltc.intr hals are populated with updated function names created in ltc intr unit. Converted all "unsigned int" usage to "u32" in ltc and ltc intr units to match with hardware 32 bit register read/write. JIRA NVGPU-3042 JIRA NVGPU-2044 Change-Id: I8684dfcc8ae343e4588b93f2b0ccde0e227635df Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2081140 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
54 lines
2.1 KiB
C
54 lines
2.1 KiB
C
/*
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* GM20B L2
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_LTC_GM20B
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#define NVGPU_LTC_GM20B
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#include <nvgpu/types.h>
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struct gk20a;
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struct gr_gk20a;
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int gm20b_determine_L2_size_bytes(struct gk20a *g);
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void gm20b_ltc_set_zbc_color_entry(struct gk20a *g,
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u32 *color_l2,
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u32 index);
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void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g,
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u32 depth_val,
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u32 index);
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void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled);
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void gm20b_ltc_init_fs_state(struct gk20a *g);
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void gm20b_flush_ltc(struct gk20a *g);
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bool gm20b_ltc_pri_is_ltc_addr(struct gk20a *g, u32 addr);
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bool gm20b_ltc_is_ltcs_ltss_addr(struct gk20a *g, u32 addr);
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bool gm20b_ltc_is_ltcn_ltss_addr(struct gk20a *g, u32 addr);
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void gm20b_ltc_split_lts_broadcast_addr(struct gk20a *g, u32 addr,
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u32 *priv_addr_table,
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u32 *priv_addr_table_index);
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void gm20b_ltc_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
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u32 *priv_addr_table,
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u32 *priv_addr_table_index);
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#endif
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