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Many tests used various incarnations of the mock register framework. This was based on a dump of gv11b registers. Tests that greatly benefitted from having generally sane register values all rely heavily on this framework. However, every test essentially did their own thing. This was not efficient and has caused a some issues in cleaning up the device and host code. Therefore introduce a much leaner and simplified register framework. All unit tests now automatically get a good subset of the gv11b registers auto-populated. As part of this also populate the HAL with a nvgpu_detect_chip() call. Many tests can now _probably_ have all their HAL init (except dummy HAL stuff) deleted. But this does require a few fixups here and there to set HALs to NULL where tests expect HALs to be NULL by default. Where necessary HALs are cleared with a memset to prevent unwanted code from executing. Overall, this imposes a far smaller burden on tests to initialize their environments. Something to consider for the future, though, is how to handle supporting multiple chips in the unit test world. JIRA NVGPU-5422 Change-Id: Icf1a63f728e9c5671ee0fdb726c235ffbd2843e2 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335334 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
305 lines
7.1 KiB
C
305 lines
7.1 KiB
C
/*
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <unistd.h>
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#include <stdlib.h>
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#include <pthread.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/types.h>
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#include <nvgpu/atomic.h>
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#include <nvgpu/nvgpu_common.h>
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#include <nvgpu/nvgpu_init.h>
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#include <nvgpu/hal_init.h>
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#include <nvgpu/os_sched.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/posix/probe.h>
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#include <nvgpu/posix/mock-regs.h>
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#include <nvgpu/posix/io.h>
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#include "os_posix.h"
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#ifdef NVGPU_UNITTEST_FAULT_INJECTION_ENABLEMENT
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#include <nvgpu/posix/posix-fault-injection.h>
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#endif
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#ifdef NVGPU_UNITTEST_FAULT_INJECTION_ENABLEMENT
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struct nvgpu_posix_fault_inj *nvgpu_nvgpu_get_fault_injection(void)
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{
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struct nvgpu_posix_fault_inj_container *c =
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nvgpu_posix_fault_injection_get_container();
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return &c->nvgpu_fi;
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}
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#endif
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/*
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* Write callback. Forward the write access to the mock IO framework.
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*/
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static void writel_access_reg_fn(struct gk20a *g,
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struct nvgpu_reg_access *access)
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{
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nvgpu_posix_io_writel_reg_space(g, access->addr, access->value);
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}
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/*
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* Read callback. Get the register value from the mock IO framework.
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*/
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static void readl_access_reg_fn(struct gk20a *g,
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struct nvgpu_reg_access *access)
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{
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access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
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}
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static struct nvgpu_posix_io_callbacks default_posix_reg_callbacks = {
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/* Write APIs all can use the same accessor. */
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.writel = writel_access_reg_fn,
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.writel_check = writel_access_reg_fn,
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.bar1_writel = writel_access_reg_fn,
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.usermode_writel = writel_access_reg_fn,
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/* Likewise for the read APIs. */
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.__readl = readl_access_reg_fn,
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.readl = readl_access_reg_fn,
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.bar1_readl = readl_access_reg_fn,
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};
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/*
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* Somewhat meaningless in userspace...
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*/
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void nvgpu_kernel_restart(void *cmd)
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{
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BUG();
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}
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void nvgpu_start_gpu_idle(struct gk20a *g)
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{
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nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
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}
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int nvgpu_enable_irqs(struct gk20a *g)
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{
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g->mc.irqs_enabled = true;
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return 0;
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}
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void nvgpu_disable_irqs(struct gk20a *g)
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{
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g->mc.irqs_enabled = false;
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}
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void nvgpu_set_power_state(struct gk20a *g, u32 state)
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{
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nvgpu_spinlock_acquire(&g->power_spinlock);
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g->power_on_state = state;
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nvgpu_spinlock_release(&g->power_spinlock);
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}
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const char *nvgpu_get_power_state(struct gk20a *g)
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{
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const char *str = NULL;
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u32 state;
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nvgpu_spinlock_acquire(&g->power_spinlock);
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state = g->power_on_state;
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nvgpu_spinlock_release(&g->power_spinlock);
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switch (state) {
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case NVGPU_STATE_POWERED_OFF:
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str = "off";
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break;
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case NVGPU_STATE_POWERING_ON:
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str = "powering on";
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break;
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case NVGPU_STATE_POWERED_ON:
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str = "on";
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break;
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default:
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nvgpu_err(g, "Invalid nvgpu power state.");
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break;
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}
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return str;
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}
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bool nvgpu_is_powered_on(struct gk20a *g)
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{
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u32 power_on;
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nvgpu_spinlock_acquire(&g->power_spinlock);
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power_on = g->power_on_state;
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nvgpu_spinlock_release(&g->power_spinlock);
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return power_on == NVGPU_STATE_POWERED_ON;
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}
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bool nvgpu_is_powered_off(struct gk20a *g)
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{
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u32 power_on;
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nvgpu_spinlock_acquire(&g->power_spinlock);
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power_on = g->power_on_state;
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nvgpu_spinlock_release(&g->power_spinlock);
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return power_on == NVGPU_STATE_POWERED_OFF;
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}
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/*
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* We have no runtime PM stuff in userspace so these are really just noops.
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*/
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void gk20a_busy_noresume(struct gk20a *g)
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{
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}
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void gk20a_idle_nosuspend(struct gk20a *g)
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{
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}
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int gk20a_busy(struct gk20a *g)
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{
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#ifdef NVGPU_UNITTEST_FAULT_INJECTION_ENABLEMENT
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if (nvgpu_posix_fault_injection_handle_call(
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nvgpu_nvgpu_get_fault_injection())) {
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return -ENODEV;
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}
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#endif
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nvgpu_atomic_inc(&g->usage_count);
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return 0;
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}
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void gk20a_idle(struct gk20a *g)
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{
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nvgpu_atomic_dec(&g->usage_count);
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}
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static void nvgpu_posix_load_regs(struct gk20a *g)
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{
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u32 i;
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int err;
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struct nvgpu_mock_iospace space;
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struct nvgpu_posix_io_reg_space *regs;
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for (i = 0; i < MOCK_REGS_LAST; i++) {
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err = nvgpu_get_mock_reglist(g, i, &space);
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if (err) {
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nvgpu_err(g, "Unknown IO regspace: %d; ignoring.", i);
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continue;
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}
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err = nvgpu_posix_io_add_reg_space(g, space.base, space.size);
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nvgpu_assert(err == 0);
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regs = nvgpu_posix_io_get_reg_space(g, space.base);
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nvgpu_assert(regs != NULL);
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if (space.data != NULL) {
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memcpy(regs->data, space.data, space.size);
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}
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}
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}
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/*
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* This function aims to initialize enough stuff to make unit testing worth
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* while. There are several interfaces and APIs that rely on the struct gk20a's
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* state in order to function: logging, for example, but there are many other
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* things, too.
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*
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* Initialize as much of that as possible here. This is meant to be equivalent
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* to the kernel space driver's probe function.
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*/
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struct gk20a *nvgpu_posix_probe(void)
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{
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struct gk20a *g;
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struct nvgpu_os_posix *p;
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#ifdef NVGPU_UNITTEST_FAULT_INJECTION_ENABLEMENT
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if (nvgpu_posix_fault_injection_handle_call(
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nvgpu_nvgpu_get_fault_injection())) {
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return NULL;
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}
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#endif
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p = malloc(sizeof(*p));
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if (p == NULL) {
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return NULL;
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}
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(void) memset(p, 0, sizeof(*p));
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g = &p->g;
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g->log_mask = 0;
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g->mm.g = g;
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if (nvgpu_kmem_init(g) != 0) {
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goto fail_kmem;
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}
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if (nvgpu_init_enabled_flags(g) != 0) {
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goto fail_enabled_flags;
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}
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/*
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* Initialize a bunch of gv11b register values.
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*/
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nvgpu_posix_io_init_reg_space(g);
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nvgpu_posix_load_regs(g);
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/*
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* Set up some default register IO callbacks that basically all
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* unit tests will be OK with. Unit tests that wish to override this
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* may do so.
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*
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* This needs to happen before the nvgpu_detect_chip() call below
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* otherise we bug out when trying to do a register read.
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*/
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(void)nvgpu_posix_register_io(g, &default_posix_reg_callbacks);
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/*
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* Detect chip based on the regs we filled above. Most unit tests
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* will be fine with this; a few may have to undo a little bit of it
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* in roder to fully test the nvgpu_detect_chip() function.
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*/
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nvgpu_assert(nvgpu_detect_chip(g) == 0);
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return g;
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fail_enabled_flags:
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nvgpu_kmem_fini(g, 0);
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fail_kmem:
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free(p);
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return NULL;
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}
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void nvgpu_posix_cleanup(struct gk20a *g)
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{
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struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
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nvgpu_kmem_fini(g, 0);
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nvgpu_free_enabled_flags(g);
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free(p);
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}
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