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5f0fdf085c
Many tests used various incarnations of the mock register framework. This was based on a dump of gv11b registers. Tests that greatly benefitted from having generally sane register values all rely heavily on this framework. However, every test essentially did their own thing. This was not efficient and has caused a some issues in cleaning up the device and host code. Therefore introduce a much leaner and simplified register framework. All unit tests now automatically get a good subset of the gv11b registers auto-populated. As part of this also populate the HAL with a nvgpu_detect_chip() call. Many tests can now _probably_ have all their HAL init (except dummy HAL stuff) deleted. But this does require a few fixups here and there to set HALs to NULL where tests expect HALs to be NULL by default. Where necessary HALs are cleared with a memset to prevent unwanted code from executing. Overall, this imposes a far smaller burden on tests to initialize their environments. Something to consider for the future, though, is how to handle supporting multiple chips in the unit test world. JIRA NVGPU-5422 Change-Id: Icf1a63f728e9c5671ee0fdb726c235ffbd2843e2 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335334 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
86 lines
2.3 KiB
C
86 lines
2.3 KiB
C
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <stdlib.h>
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#include <unistd.h>
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#include <unit/io.h>
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#include <nvgpu/posix/io.h>
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#include <nvgpu/posix/soc_fuse.h>
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#include <nvgpu/posix/mock-regs.h>
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#include <nvgpu/gk20a.h>
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#include "hal/fuse/fuse_gm20b.h"
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#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
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#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
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#include "nvgpu-gr-gv11b.h"
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#define NUM_REG_SPACES 1U
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static struct nvgpu_mock_iospace reg_spaces[NUM_REG_SPACES] = {
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[0] = { /* NV_PLTCG_LTCS_REGSPACE */
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.base = 0x17E200,
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.size = 0x100,
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.data = NULL,
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},
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};
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static void delete_reg_space(struct unit_module *m, struct gk20a *g)
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{
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u32 i = 0;
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for (i = 0; i < NUM_REG_SPACES; i++) {
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nvgpu_posix_io_delete_reg_space(g, reg_spaces[i].base);
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}
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}
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static int add_reg_space(struct unit_module *m, struct gk20a *g)
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{
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u32 i;
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int err;
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for (i = 0; i < NUM_REG_SPACES; i++) {
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struct nvgpu_mock_iospace *iospace = ®_spaces[i];
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err = nvgpu_posix_io_add_reg_space(g, iospace->base,
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iospace->size);
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nvgpu_assert(err == 0);
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}
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return 0;
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}
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int test_gr_setup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
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{
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nvgpu_assert(add_reg_space(m, g) == 0);
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return 0;
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}
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void test_gr_cleanup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
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{
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delete_reg_space(m, g);
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}
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