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e140d72ff8
Added pre-populated register spaces for gv11b: - NV_PFIFO 0x00003FFF:0x00002000 - NV_PTOP 0x000227FF:0x00022400 Registers values were captured on DDPX with reg_dump, after disabling railgating and ELPG. This allows running nvgpu_fifo_init_support, using gv11b HALs. Added the following tests: - test_fifo_init_support - test_tsg_open - test_tsg_release - test_fifo_remove_support Jira NVGPU-3476 Change-Id: Ia717d9a9d431248635d51d0c265c16c2b6806a95 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2120564 GVS: Gerrit_Virtual_Submit Reviewed-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>