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3e43f92f21
Mass copy ga10b & ga100 sources from nvgpu-next repo. TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1 Jira NVGPU-4771 Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831 Signed-off-by: Sagar Kadamati <skadamati@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
64 lines
2.2 KiB
C
64 lines
2.2 KiB
C
/*
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* GA10B FB
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*
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* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_FB_GA10B_H
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#define NVGPU_FB_GA10B_H
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#define VPR_INFO_FETCH_POLL_MS 5U
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#define ALIGN_HI32(x) nvgpu_safe_sub_u32(32U, (x))
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struct gk20a;
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void ga10b_fb_init_fs_state(struct gk20a *g);
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void ga10b_fb_init_hw(struct gk20a *g);
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u32 ga10b_fb_get_num_active_ltcs(struct gk20a *g);
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void ga10b_fb_dump_vpr_info(struct gk20a *g);
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void ga10b_fb_dump_wpr_info(struct gk20a *g);
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void ga10b_fb_read_wpr_info(struct gk20a *g, u64 *wpr_base, u64 *wpr_size);
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int ga10b_fb_vpr_info_fetch(struct gk20a *g);
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#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
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#if defined(__KERNEL__)
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void ga10b_init_nvlink_soc_credits(struct gk20a *g);
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#else
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static inline void ga10b_init_nvlink_soc_credits(struct gk20a *g)
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{
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}
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#endif
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#endif
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#ifdef CONFIG_NVGPU_COMPRESSION
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void ga10b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc);
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#endif
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#ifdef CONFIG_NVGPU_MIG
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int ga10b_fb_config_veid_smc_map(struct gk20a *g, bool enable);
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int ga10b_fb_set_smc_eng_config(struct gk20a *g, bool enable);
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int ga10b_fb_set_remote_swizid(struct gk20a *g, bool enable);
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#endif
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int ga10b_fb_set_atomic_mode(struct gk20a *g);
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#endif /* NVGPU_FB_GA10B_H */
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