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3e43f92f21
Mass copy ga10b & ga100 sources from nvgpu-next repo. TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1 Jira NVGPU-4771 Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831 Signed-off-by: Sagar Kadamati <skadamati@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
68 lines
2.1 KiB
C
68 lines
2.1 KiB
C
/*
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* GA100 FUSE
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*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/types.h>
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#include <nvgpu/io.h>
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#include <nvgpu/falcon.h>
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#include "fuse_ga100.h"
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#include <nvgpu/hw/ga100/hw_fuse_ga100.h>
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u32 ga100_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp)
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{
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return nvgpu_readl(g, fuse_status_opt_rop_l2_fbp_r(fbp));
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}
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int ga100_fuse_read_per_device_identifier(struct gk20a *g, u64 *pdi)
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{
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u32 lo = nvgpu_readl(g, fuse_opt_pdi_0_r());
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u32 hi = nvgpu_readl(g, fuse_opt_pdi_1_r());
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*pdi = ((u64)lo) | (((u64)hi) << 32);
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return 0;
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}
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int ga100_read_ucode_version(struct gk20a *g, u32 falcon_id, u32 *ucode_version)
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{
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u32 err = 0;
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switch (falcon_id) {
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case FALCON_ID_GSPLITE:
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*ucode_version = nvgpu_readl(g, fuse_gsp_ucode1_version_r());
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break;
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case FALCON_ID_SEC2:
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*ucode_version = nvgpu_readl(g, fuse_sec2_ucode1_version_r());
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break;
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default:
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err = -EINVAL;
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nvgpu_err(g, "Invalid/Unsupported falcon ID %x", falcon_id);
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break;
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}
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return err;
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}
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