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3e43f92f21
Mass copy ga10b & ga100 sources from nvgpu-next repo. TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1 Jira NVGPU-4771 Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831 Signed-off-by: Sagar Kadamati <skadamati@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
81 lines
2.7 KiB
C
81 lines
2.7 KiB
C
/*
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* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gr/zbc.h>
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#include "ltc_ga10b.h"
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#include <nvgpu/hw/ga10b/hw_ltc_ga10b.h>
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void ga10b_ltc_set_zbc_stencil_entry(struct gk20a *g, u32 stencil_depth,
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u32 index)
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{
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nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
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ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
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nvgpu_writel(g,
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ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(), stencil_depth);
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}
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void ga10b_ltc_set_zbc_color_entry(struct gk20a *g, u32 *color_l2, u32 index)
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{
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u32 i;
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nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
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ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
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for (i = 0; i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v();
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i++) {
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nvgpu_writel(g,
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ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i),
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color_l2[i]);
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}
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}
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/*
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* Sets the ZBC depth for the passed index.
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*/
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void ga10b_ltc_set_zbc_depth_entry(struct gk20a *g, u32 depth_val, u32 index)
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{
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nvgpu_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
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ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
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nvgpu_writel(g,
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ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(), depth_val);
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}
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u32 ga10b_ltc_pri_shared_addr(struct gk20a *g, u32 addr)
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{
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u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
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u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
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u32 ltc_shared_base = ltc_ltcs_ltss_v();
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u32 ltc_addr_mask = nvgpu_safe_sub_u32(ltc_stride, 1);
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u32 lts_addr_mask = nvgpu_safe_sub_u32(lts_stride, 1);
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u32 ltc_addr = addr & ltc_addr_mask;
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u32 lts_addr = ltc_addr & lts_addr_mask;
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return ltc_shared_base + lts_addr;
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}
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