Philip Elcan 629a8de6c4 gpu: nvgpu: posix: make U*_MAX MISRA-friendly ...

The POSIX definitions of U8_MAX, U16_MAX, U32_MAX, and U64_MAX in use
was causing a MISRA 10.8 violation because the value 0U was being used
as an 8-bit value per the spec. This updates the definitions to cast 0
to the appropriate bit width instead of using 0U. This eliminates the
MISRA violation.

JIRA NVGPU-2955

Change-Id: Ib3220df8c08566b4594136f8a7deb0dec8b01ab3
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2078364
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2019-03-22 08:47:36 -07:00

..

nvgpu

gpu: nvgpu: posix: make U*_MAX MISRA-friendly

2019-03-22 08:47:36 -07:00