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c6cfb12d91
MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: Id3b2c8ea1af1807087468c6978abfbfc85bee2ec Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809757 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
137 lines
4.0 KiB
C
137 lines
4.0 KiB
C
/*
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* general power channel structures & definitions
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*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PMGR_PWRPOLICY_H
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#define NVGPU_PMGR_PWRPOLICY_H
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#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
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#include "boardobj/boardobjgrp.h"
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#include "boardobj/boardobj.h"
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#include "ctrl/ctrlpmgr.h"
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#define PWR_POLICY_EXT_POWER_STATE_ID_COUNT 0x4U
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enum pwr_policy_limit_id {
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PWR_POLICY_LIMIT_ID_MIN = 0x00000000,
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PWR_POLICY_LIMIT_ID_RATED,
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PWR_POLICY_LIMIT_ID_MAX,
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PWR_POLICY_LIMIT_ID_CURR,
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PWR_POLICY_LIMIT_ID_BATT,
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};
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struct pwr_policy {
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struct boardobj super;
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u8 ch_idx;
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u8 num_limit_inputs;
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u8 limit_unit;
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s32 limit_delta;
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u32 limit_min;
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u32 limit_rated;
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u32 limit_max;
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u32 limit_batt;
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struct ctrl_pmgr_pwr_policy_info_integral integral;
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struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_min;
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struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_rated;
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struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_max;
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struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_batt;
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struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_curr;
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u8 sample_mult;
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enum ctrl_pmgr_pwr_policy_filter_type filter_type;
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union ctrl_pmgr_pwr_policy_filter_param filter_param;
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};
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struct pwr_policy_ext_limit {
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u8 policy_table_idx;
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u32 limit;
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};
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struct pwr_policy_batt_workitem {
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u32 power_state;
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bool b_full_deflection;
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};
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struct pwr_policy_client_workitem {
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u32 limit;
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bool b_pending;
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};
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struct pwr_policy_relationship {
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struct boardobj super;
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u8 policy_idx;
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};
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struct pmgr_pwr_policy {
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u8 version;
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bool b_enabled;
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struct nv_pmu_perf_domain_group_limits global_ceiling;
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u8 policy_idxs[CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES];
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struct pwr_policy_ext_limit ext_limits[PWR_POLICY_EXT_POWER_STATE_ID_COUNT];
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s32 ext_power_state;
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u16 base_sample_period;
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u16 min_client_sample_period;
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u8 low_sampling_mult;
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struct boardobjgrp_e32 pwr_policies;
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struct boardobjgrp_e32 pwr_policy_rels;
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struct boardobjgrp_e32 pwr_violations;
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struct pwr_policy_client_workitem client_work_item;
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};
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struct pwr_policy_limit {
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struct pwr_policy super;
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};
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struct pwr_policy_hw_threshold {
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struct pwr_policy_limit super;
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u8 threshold_idx;
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u8 low_threshold_idx;
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bool b_use_low_threshold;
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u16 low_threshold_value;
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};
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struct pwr_policy_sw_threshold {
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struct pwr_policy_limit super;
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u8 threshold_idx;
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u8 low_threshold_idx;
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bool b_use_low_threshold;
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u16 low_threshold_value;
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u8 event_id;
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};
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union pwr_policy_data_union {
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struct boardobj boardobj;
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struct pwr_policy pwrpolicy;
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struct pwr_policy_hw_threshold hw_threshold;
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struct pwr_policy_sw_threshold sw_threshold;
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} ;
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#define PMGR_GET_PWR_POLICY(g, policy_idx) \
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((struct pwr_policy *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
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&(g->pmgr_pmu.pmgr_policyobjs.pwr_policies.super), (policy_idx)))
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#define PMGR_PWR_POLICY_INCREMENT_LIMIT_INPUT_COUNT(ppolicy) \
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((ppolicy)->num_limit_inputs++)
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int pmgr_policy_sw_setup(struct gk20a *g);
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#endif /* NVGPU_PMGR_PWRPOLICY_H */
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