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a3ba265dd6
MISRA Rule 10.3 prohibits implicit assignment of objects of different size or essential type. This resolves a number of 10.3 violations in the nvgpu/common/mm unit. JIRA NVGPU-2935 Change-Id: Ic9d826bf67417962aab433d08d3e922de26e3edc Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2036117 GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
66 lines
2.3 KiB
C
66 lines
2.3 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PD_CACHE_H
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#define NVGPU_PD_CACHE_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct vm_gk20a;
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struct nvgpu_mem;
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struct gk20a_mmu_level;
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/*
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* GMMU page directory. This is the kernel's tracking of a list of PDEs or PTEs
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* in the GMMU.
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*/
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struct nvgpu_gmmu_pd {
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/*
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* DMA memory describing the PTEs or PDEs. @mem_offs describes the
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* offset of the PDE table in @mem. @cached specifies if this PD is
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* using pd_cache memory.
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*/
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struct nvgpu_mem *mem;
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u32 mem_offs;
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bool cached;
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u32 pd_size; /* In bytes. */
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/*
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* List of pointers to the next level of page tables. Does not
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* need to be populated when this PD is pointing to PTEs.
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*/
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struct nvgpu_gmmu_pd *entries;
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u32 num_entries;
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};
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int nvgpu_pd_alloc(struct vm_gk20a *vm, struct nvgpu_gmmu_pd *pd, u32 bytes);
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void nvgpu_pd_free(struct vm_gk20a *vm, struct nvgpu_gmmu_pd *pd);
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int nvgpu_pd_cache_init(struct gk20a *g);
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void nvgpu_pd_cache_fini(struct gk20a *g);
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u32 nvgpu_pd_offset_from_index(const struct gk20a_mmu_level *l, u32 pd_idx);
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void nvgpu_pd_write(struct gk20a *g, struct nvgpu_gmmu_pd *pd,
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size_t w, u32 data);
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u64 nvgpu_pd_gpu_addr(struct gk20a *g, struct nvgpu_gmmu_pd *pd);
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#endif
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