mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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4739499f07
Synchronize gk20a and gm20b headers. All registers which were added to gk20a are now added to gm20b, and some registers that are unused are removed. Bug 1567274 Change-Id: Ia3b7958c148e495cbff420ee56bb448db0f58680 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/590313 GVS: Gerrit_Virtual_Submit
438 lines
11 KiB
C
438 lines
11 KiB
C
/*
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* Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Function naming determines intended use:
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*
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* <x>_r(void) : Returns the offset for register <x>.
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*
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* <x>_o(void) : Returns the offset for element <x>.
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*
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* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
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*
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* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
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*
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* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
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* and masked to place it at field <y> of register <x>. This value
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* can be |'d with others to produce a full register value for
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* register <x>.
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*
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* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
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* value can be ~'d and then &'d to clear the value of field <y> for
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* register <x>.
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*
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* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
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* to place it at field <y> of register <x>. This value can be |'d
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* with others to produce a full register value for <x>.
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*
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* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
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* <x> value 'r' after being shifted to place its LSB at bit 0.
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* This value is suitable for direct comparison with other unshifted
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* values appropriate for use in field <y> of register <x>.
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*
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* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
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* field <y> of register <x>. This value is suitable for direct
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef _hw_ltc_gk20a_h_
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#define _hw_ltc_gk20a_h_
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static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
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{
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return 0x001410c8;
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}
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static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
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{
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return 0x00141200;
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}
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static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
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{
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return 0x0017ea00;
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}
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static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
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{
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return 0x00141104;
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}
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static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
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{
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return (r >> 0) & 0xffff;
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}
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static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
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{
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return (r >> 16) & 0x3;
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}
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static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
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{
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return 0x00000000;
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}
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static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
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{
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return 0x00000001;
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}
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static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
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{
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return 0x00000002;
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}
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static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
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{
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return 0x0017e8c8;
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}
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static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
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{
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return 0x1;
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}
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static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
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{
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return 0x2;
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}
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static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
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{
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return (r >> 2) & 0x1;
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}
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static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
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{
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return 0x00000001;
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}
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static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
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{
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return 0x4;
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}
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static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
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{
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return 0x001410c8;
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}
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static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
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{
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return 0x0017e8cc;
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}
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static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
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{
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return (v & 0x1ffff) << 0;
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}
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static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
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{
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return 0x0017e8d0;
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}
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static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
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{
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return (v & 0x1ffff) << 0;
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}
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static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
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{
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return 0x0001ffff;
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}
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static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
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{
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return 0x0017e8d4;
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}
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static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
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{
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return 0x0000000b;
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}
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static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
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{
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return (r >> 0) & 0x3ffffff;
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}
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static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
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{
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return 0x0017e8dc;
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}
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static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
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{
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return (r >> 0) & 0xffff;
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}
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static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
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{
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return (r >> 24) & 0xf;
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}
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static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(u32 r)
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{
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return (r >> 28) & 0xf;
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}
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static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
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{
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return 0x0017e91c;
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}
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static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
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{
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return (v & 0x1f) << 16;
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}
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static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
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{
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return 0x0017ea44;
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}
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static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
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{
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return (v & 0xf) << 0;
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}
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static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
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{
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return 0x0017ea48 + i*4;
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}
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static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
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{
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return 0x00000004;
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}
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static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
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{
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return 0x0017ea58;
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}
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static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
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{
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return 32;
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}
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static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
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{
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return (v & 0xffffffff) << 0;
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}
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static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
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{
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return 0xffffffff << 0;
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}
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static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
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{
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return (r >> 0) & 0xffffffff;
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}
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static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
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{
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return 0x0017e924;
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}
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static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
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{
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return 0x10000000;
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}
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static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
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{
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return 0x0017e828;
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}
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static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
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{
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return (r >> 0) & 0x1;
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}
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static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
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{
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return 0x00000001;
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}
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static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
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{
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return 0x1;
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}
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static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
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{
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return 0x00140828;
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}
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static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
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{
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return (r >> 0) & 0x1;
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}
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static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
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{
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return 0x00000001;
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}
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static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
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{
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return 0x1;
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}
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static inline u32 ltc_ltc0_ltss_intr_r(void)
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{
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return 0x00140820;
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}
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static inline u32 ltc_ltcs_ltss_intr_r(void)
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{
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return 0x0017e820;
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}
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static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
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{
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return 0x1 << 20;
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}
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static inline u32 ltc_ltc0_lts0_intr_r(void)
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{
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return 0x00141020;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
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{
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return 0x0017e910;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
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{
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return (r >> 0) & 0x1;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
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{
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return 0x00000001;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
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{
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return 0x1;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
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{
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return (r >> 8) & 0xf;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
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{
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return 0x00000003;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
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{
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return 0x300;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
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{
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return (r >> 28) & 0x1;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
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{
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return 0x00000001;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
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{
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return 0x10000000;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
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{
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return (r >> 29) & 0x1;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
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{
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return 0x00000001;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
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{
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return 0x20000000;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
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{
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return (r >> 30) & 0x1;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
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{
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return 0x00000001;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
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{
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return 0x40000000;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
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{
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return 0x0017e914;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
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{
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return (r >> 0) & 0x1;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
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{
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return 0x00000001;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
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{
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return 0x1;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
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{
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return (r >> 8) & 0xf;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
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{
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return 0x00000003;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
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{
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return 0x300;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
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{
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return (r >> 16) & 0x1;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
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{
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return 0x00000001;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
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{
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return 0x10000;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
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{
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return (r >> 28) & 0x1;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
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{
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return 0x00000001;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
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{
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return 0x10000000;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
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{
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return (r >> 29) & 0x1;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
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{
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return 0x00000001;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
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{
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return 0x20000000;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
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{
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return (r >> 30) & 0x1;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
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{
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return 0x00000001;
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}
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static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
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{
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return 0x40000000;
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}
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static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
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{
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return 0x00140910;
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}
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static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
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{
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return (r >> 0) & 0x1;
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}
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static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
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{
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return 0x00000001;
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}
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static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
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{
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return 0x1;
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}
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static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
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{
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return 0x00140914;
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}
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static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
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{
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return (r >> 0) & 0x1;
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}
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static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
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{
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return 0x00000001;
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}
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static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
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{
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return 0x1;
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}
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#endif
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