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6ac3fc30c7
Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in common.gr.ctx unit. Jira NVGPU-3506 Change-Id: I42becd6404eb12b39dca7815849425128e7e42d8 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2132256 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
252 lines
8.7 KiB
C
252 lines
8.7 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_INCLUDE_GR_CTX_H
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#define NVGPU_INCLUDE_GR_CTX_H
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#include <nvgpu/types.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/gr/global_ctx.h>
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/*
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* allocate a minimum of 1 page (4KB) worth of patch space, this is 512 entries
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* of address and data pairs
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*/
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#define PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY 2U
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#define PATCH_CTX_SLOTS_PER_PAGE \
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(PAGE_SIZE/(PATCH_CTX_SLOTS_REQUIRED_PER_ENTRY * (u32)sizeof(u32)))
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#define PATCH_CTX_ENTRIES_FROM_SIZE(size) ((size)/sizeof(u32))
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#define NVGPU_PREEMPTION_MODE_GRAPHICS_WFI BIT32(0)
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#define NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP BIT32(1)
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#define NVGPU_PREEMPTION_MODE_COMPUTE_WFI BIT32(0)
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#define NVGPU_PREEMPTION_MODE_COMPUTE_CTA BIT32(1)
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#define NVGPU_PREEMPTION_MODE_COMPUTE_CILP BIT32(2)
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struct gk20a;
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struct vm_gk20a;
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struct nvgpu_gr_ctx;
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struct nvgpu_gr_global_ctx_buffer_desc;
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struct nvgpu_gr_global_ctx_local_golden_image;
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struct patch_desc;
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struct pm_ctx_desc;
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struct nvgpu_gr_ctx_desc;
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#ifdef CONFIG_NVGPU_GRAPHICS
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struct zcull_ctx_desc;
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#endif
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#define NVGPU_GR_CTX_CTX 0U
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#ifdef CONFIG_NVGPU_DEBUGGER
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#define NVGPU_GR_CTX_PM_CTX 1U
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#endif
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#define NVGPU_GR_CTX_PATCH_CTX 2U
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#define NVGPU_GR_CTX_PREEMPT_CTXSW 3U
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#define NVGPU_GR_CTX_SPILL_CTXSW 4U
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#define NVGPU_GR_CTX_BETACB_CTXSW 5U
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#define NVGPU_GR_CTX_PAGEPOOL_CTXSW 6U
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#define NVGPU_GR_CTX_GFXP_RTVCB_CTXSW 7U
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#define NVGPU_GR_CTX_COUNT 8U
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/*
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* either ATTRIBUTE or ATTRIBUTE_VPR maps to NVGPU_GR_CTX_ATTRIBUTE_VA
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*/
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#define NVGPU_GR_CTX_CIRCULAR_VA 0U
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#define NVGPU_GR_CTX_PAGEPOOL_VA 1U
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#define NVGPU_GR_CTX_ATTRIBUTE_VA 2U
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#define NVGPU_GR_CTX_PRIV_ACCESS_MAP_VA 3U
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#define NVGPU_GR_CTX_RTV_CIRCULAR_BUFFER_VA 4U
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#ifdef CONFIG_NVGPU_FECS_TRACE
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#define NVGPU_GR_CTX_FECS_TRACE_BUFFER_VA 5U
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#endif
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#define NVGPU_GR_CTX_VA_COUNT 6U
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#ifdef CONFIG_NVGPU_DEBUGGER
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/* PM Context Switch Mode */
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/*This mode says that the pms are not to be context switched. */
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#define NVGPU_GR_CTX_HWPM_CTXSW_MODE_NO_CTXSW (0x00000000U)
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/* This mode says that the pms in Mode-B are to be context switched */
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#define NVGPU_GR_CTX_HWPM_CTXSW_MODE_CTXSW (0x00000001U)
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/* This mode says that the pms in Mode-E (stream out) are to be context switched. */
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#define NVGPU_GR_CTX_HWPM_CTXSW_MODE_STREAM_OUT_CTXSW (0x00000002U)
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#endif
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struct nvgpu_gr_ctx_desc *nvgpu_gr_ctx_desc_alloc(struct gk20a *g);
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void nvgpu_gr_ctx_desc_free(struct gk20a *g,
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struct nvgpu_gr_ctx_desc *desc);
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void nvgpu_gr_ctx_set_size(struct nvgpu_gr_ctx_desc *gr_ctx_desc,
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u32 index, u32 size);
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int nvgpu_gr_ctx_alloc(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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struct nvgpu_gr_ctx_desc *gr_ctx_desc,
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struct vm_gk20a *vm);
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void nvgpu_gr_ctx_free(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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struct nvgpu_gr_global_ctx_buffer_desc *global_ctx_buffer,
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struct vm_gk20a *vm);
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int nvgpu_gr_ctx_alloc_patch_ctx(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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struct nvgpu_gr_ctx_desc *gr_ctx_desc,
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struct vm_gk20a *vm);
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void nvgpu_gr_ctx_free_patch_ctx(struct gk20a *g, struct vm_gk20a *vm,
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struct nvgpu_gr_ctx *gr_ctx);
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int nvgpu_gr_ctx_alloc_ctxsw_buffers(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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struct nvgpu_gr_ctx_desc *gr_ctx_desc,
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struct vm_gk20a *vm);
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int nvgpu_gr_ctx_map_global_ctx_buffers(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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struct nvgpu_gr_global_ctx_buffer_desc *global_ctx_buffer,
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struct vm_gk20a *vm, bool vpr);
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u64 nvgpu_gr_ctx_get_global_ctx_va(struct nvgpu_gr_ctx *gr_ctx,
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u32 index);
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struct nvgpu_mem *nvgpu_gr_ctx_get_spill_ctxsw_buffer(
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struct nvgpu_gr_ctx *gr_ctx);
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struct nvgpu_mem *nvgpu_gr_ctx_get_betacb_ctxsw_buffer(
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struct nvgpu_gr_ctx *gr_ctx);
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struct nvgpu_mem *nvgpu_gr_ctx_get_pagepool_ctxsw_buffer(
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struct nvgpu_gr_ctx *gr_ctx);
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struct nvgpu_mem *nvgpu_gr_ctx_get_preempt_ctxsw_buffer(
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struct nvgpu_gr_ctx *gr_ctx);
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struct nvgpu_mem *nvgpu_gr_ctx_get_gfxp_rtvcb_ctxsw_buffer(
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struct nvgpu_gr_ctx *gr_ctx);
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struct nvgpu_mem *nvgpu_gr_ctx_get_patch_ctx_mem(struct nvgpu_gr_ctx *gr_ctx);
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void nvgpu_gr_ctx_set_patch_ctx_data_count(struct nvgpu_gr_ctx *gr_ctx,
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u32 data_count);
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struct nvgpu_mem *nvgpu_gr_ctx_get_ctx_mem(struct nvgpu_gr_ctx *gr_ctx);
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int nvgpu_gr_ctx_load_golden_ctx_image(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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struct nvgpu_gr_global_ctx_local_golden_image *local_golden_image,
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bool cde);
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int nvgpu_gr_ctx_patch_write_begin(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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bool update_patch_count);
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void nvgpu_gr_ctx_patch_write_end(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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bool update_patch_count);
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void nvgpu_gr_ctx_patch_write(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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u32 addr, u32 data, bool patch);
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void nvgpu_gr_ctx_reset_patch_count(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx);
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void nvgpu_gr_ctx_set_patch_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx,
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bool set_patch_addr);
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#ifdef CONFIG_NVGPU_GRAPHICS
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void nvgpu_gr_ctx_set_zcull_ctx(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx,
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u32 mode, u64 gpu_va);
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u64 nvgpu_gr_ctx_get_zcull_ctx_va(struct nvgpu_gr_ctx *gr_ctx);
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int nvgpu_gr_ctx_init_zcull(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx);
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int nvgpu_gr_ctx_zcull_setup(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx,
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bool set_zcull_ptr);
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#endif
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void nvgpu_gr_ctx_init_compute_preemption_mode(struct nvgpu_gr_ctx *gr_ctx,
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u32 compute_preempt_mode);
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u32 nvgpu_gr_ctx_get_compute_preemption_mode(struct nvgpu_gr_ctx *gr_ctx);
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void nvgpu_gr_ctx_init_graphics_preemption_mode(struct nvgpu_gr_ctx *gr_ctx,
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u32 graphics_preempt_mode);
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u32 nvgpu_gr_ctx_get_graphics_preemption_mode(struct nvgpu_gr_ctx *gr_ctx);
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bool nvgpu_gr_ctx_check_valid_preemption_mode(struct nvgpu_gr_ctx *gr_ctx,
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u32 graphics_preempt_mode, u32 compute_preempt_mode);
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void nvgpu_gr_ctx_set_preemption_modes(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx);
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void nvgpu_gr_ctx_set_preemption_buffer_va(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx);
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struct nvgpu_gr_ctx *nvgpu_alloc_gr_ctx_struct(struct gk20a *g);
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void nvgpu_free_gr_ctx_struct(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx);
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void nvgpu_gr_ctx_set_tsgid(struct nvgpu_gr_ctx *gr_ctx, u32 tsgid);
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u32 nvgpu_gr_ctx_get_tsgid(struct nvgpu_gr_ctx *gr_ctx);
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bool nvgpu_gr_ctx_get_cilp_preempt_pending(struct nvgpu_gr_ctx *gr_ctx);
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void nvgpu_gr_ctx_set_cilp_preempt_pending(struct nvgpu_gr_ctx *gr_ctx,
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bool cilp_preempt_pending);
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bool nvgpu_gr_ctx_desc_force_preemption_gfxp(
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struct nvgpu_gr_ctx_desc *gr_ctx_desc);
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bool nvgpu_gr_ctx_desc_force_preemption_cilp(
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struct nvgpu_gr_ctx_desc *gr_ctx_desc);
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#ifdef CONFIG_NVGPU_DEBUGGER
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int nvgpu_gr_ctx_alloc_pm_ctx(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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struct nvgpu_gr_ctx_desc *gr_ctx_desc,
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struct vm_gk20a *vm,
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u64 gpu_va);
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void nvgpu_gr_ctx_free_pm_ctx(struct gk20a *g, struct vm_gk20a *vm,
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struct nvgpu_gr_ctx *gr_ctx);
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u32 nvgpu_gr_ctx_get_ctx_id(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx);
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u32 nvgpu_gr_ctx_read_ctx_id(struct nvgpu_gr_ctx *gr_ctx);
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struct nvgpu_mem *nvgpu_gr_ctx_get_pm_ctx_mem(struct nvgpu_gr_ctx *gr_ctx);
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void nvgpu_gr_ctx_set_pm_ctx_pm_mode(struct nvgpu_gr_ctx *gr_ctx, u32 pm_mode);
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u32 nvgpu_gr_ctx_get_pm_ctx_pm_mode(struct nvgpu_gr_ctx *gr_ctx);
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int nvgpu_gr_ctx_set_smpc_mode(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx,
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bool enable);
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int nvgpu_gr_ctx_prepare_hwpm_mode(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx,
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u32 mode, bool *skip_update);
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int nvgpu_gr_ctx_set_hwpm_mode(struct gk20a *g, struct nvgpu_gr_ctx *gr_ctx,
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bool set_pm_ptr);
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#ifdef CONFIG_NVGPU_CHANNEL_TSG_SCHEDULING
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void nvgpu_gr_ctx_set_boosted_ctx(struct nvgpu_gr_ctx *gr_ctx, bool boost);
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bool nvgpu_gr_ctx_get_boosted_ctx(struct nvgpu_gr_ctx *gr_ctx);
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#endif
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bool nvgpu_gr_ctx_desc_dump_ctxsw_stats_on_channel_close(
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struct nvgpu_gr_ctx_desc *gr_ctx_desc);
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#endif /* CONFIG_NVGPU_DEBUGGER */
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#endif /* NVGPU_INCLUDE_GR_CTX_H */
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