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1d9eba07c5
Bug 1500195 Change-Id: I5545d1a95a58e7daa5a74cc20f3fc6828774fc42 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/488507 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
55 lines
1.6 KiB
C
55 lines
1.6 KiB
C
/*
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*
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* Tegra GK20A GPU Debugger Driver Register Ops
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*
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* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __REGOPS_GK20A_H_
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#define __REGOPS_GK20A_H_
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#include <linux/nvhost_dbg_gpu_ioctl.h>
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struct regop_offset_range {
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u32 base:24;
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u32 count:8;
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};
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int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
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struct nvhost_dbg_gpu_reg_op *ops,
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u64 num_ops);
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/* turn seriously unwieldy names -> something shorter */
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#define REGOP(x) NVHOST_DBG_GPU_REG_OP_##x
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static inline bool reg_op_is_gr_ctx(u8 type)
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{
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return type == REGOP(TYPE_GR_CTX) ||
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type == REGOP(TYPE_GR_CTX_TPC) ||
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type == REGOP(TYPE_GR_CTX_SM) ||
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type == REGOP(TYPE_GR_CTX_CROP) ||
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type == REGOP(TYPE_GR_CTX_ZROP) ||
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type == REGOP(TYPE_GR_CTX_QUAD);
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}
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static inline bool reg_op_is_read(u8 op)
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{
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return op == REGOP(READ_32) ||
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op == REGOP(READ_64) ;
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}
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bool is_bar0_global_offset_whitelisted_gk20a(struct gk20a *g, u32 offset);
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void gk20a_init_regops(struct gpu_ops *gops);
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#endif /* __REGOPS_GK20A_H_ */
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