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d65f23cb9a
Retrieve channel count from gm20b specific header instead of the gk20a header. This increases channel count from 128 to 512. Change-Id: I96d4887432852795f7f526e33f0d3d2458f3af0e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/500623
122 lines
3.4 KiB
C
122 lines
3.4 KiB
C
/*
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* GM20B Fifo
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*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/delay.h>
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#include "gk20a/gk20a.h"
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#include "fifo_gm20b.h"
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#include "hw_ccsr_gm20b.h"
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#include "hw_ram_gm20b.h"
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#include "hw_fifo_gm20b.h"
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static void channel_gm20b_bind(struct channel_gk20a *ch_gk20a)
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{
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struct gk20a *g = ch_gk20a->g;
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u32 inst_ptr = ch_gk20a->inst_block.cpu_pa
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>> ram_in_base_shift_v();
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gk20a_dbg_info("bind channel %d inst ptr 0x%08x",
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ch_gk20a->hw_chid, inst_ptr);
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ch_gk20a->bound = true;
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gk20a_writel(g, ccsr_channel_inst_r(ch_gk20a->hw_chid),
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ccsr_channel_inst_ptr_f(inst_ptr) |
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ccsr_channel_inst_target_vid_mem_f() |
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ccsr_channel_inst_bind_true_f());
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gk20a_writel(g, ccsr_channel_r(ch_gk20a->hw_chid),
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(gk20a_readl(g, ccsr_channel_r(ch_gk20a->hw_chid)) &
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~ccsr_channel_enable_set_f(~0)) |
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ccsr_channel_enable_set_true_f());
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}
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static inline u32 gm20b_engine_id_to_mmu_id(u32 engine_id)
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{
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switch (engine_id) {
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case ENGINE_GR_GK20A:
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return 0;
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case ENGINE_CE2_GK20A:
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return 1;
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default:
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return ~0;
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}
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}
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static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
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unsigned long engine_ids)
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{
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unsigned long end_jiffies = jiffies +
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msecs_to_jiffies(gk20a_get_gr_idle_timeout(g));
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unsigned long delay = GR_IDLE_CHECK_DEFAULT;
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unsigned long engine_id;
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int ret = -EBUSY;
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/* trigger faults for all bad engines */
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for_each_set_bit(engine_id, &engine_ids, 32) {
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u32 engine_mmu_id;
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if (engine_id > g->fifo.max_engines) {
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gk20a_err(dev_from_gk20a(g),
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"faulting unknown engine %ld", engine_id);
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} else {
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engine_mmu_id = gm20b_engine_id_to_mmu_id(engine_id);
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gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_mmu_id),
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fifo_trigger_mmu_fault_enable_f(1));
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}
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}
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/* Wait for MMU fault to trigger */
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do {
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if (gk20a_readl(g, fifo_intr_0_r()) &
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fifo_intr_0_mmu_fault_pending_f()) {
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ret = 0;
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break;
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}
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usleep_range(delay, delay * 2);
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delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX);
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} while (time_before(jiffies, end_jiffies) ||
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!tegra_platform_is_silicon());
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if (ret)
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gk20a_err(dev_from_gk20a(g), "mmu fault timeout");
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/* release mmu fault trigger */
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for_each_set_bit(engine_id, &engine_ids, 32)
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gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 0);
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}
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static u32 gm20b_fifo_get_num_fifos(struct gk20a *g)
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{
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return ccsr_channel__size_1_v();
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}
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void gm20b_init_fifo(struct gpu_ops *gops)
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{
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gops->fifo.bind_channel = channel_gm20b_bind;
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gops->fifo.unbind_channel = channel_gk20a_unbind;
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gops->fifo.disable_channel = channel_gk20a_disable;
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gops->fifo.alloc_inst = channel_gk20a_alloc_inst;
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gops->fifo.free_inst = channel_gk20a_free_inst;
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gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc;
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gops->fifo.preempt_channel = gk20a_fifo_preempt_channel;
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gops->fifo.update_runlist = gk20a_fifo_update_runlist;
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gops->fifo.trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault;
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gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle;
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gops->fifo.get_num_fifos = gm20b_fifo_get_num_fifos;
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}
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