mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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8be2f2bf4c
Regenerate clock gating lists. Add new blocks, and takes them into use. Also moves some clock gating settings to be applied at the earliest possible moment right after reset. Change-Id: I21888186c200f7a477c63bd3332e8ed578f63741 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/457698
130 lines
3.5 KiB
C
130 lines
3.5 KiB
C
/*
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* GM20B Graphics
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*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/types.h>
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#include "gk20a/gk20a.h"
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#include "ltc_gm20b.h"
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#include "gr_gm20b.h"
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#include "ltc_gm20b.h"
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#include "fb_gm20b.h"
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#include "gm20b_gating_reglist.h"
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#include "fifo_gm20b.h"
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#include "gr_ctx_gm20b.h"
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#include "mm_gm20b.h"
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#include "pmu_gm20b.h"
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#include "clk_gm20b.h"
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#include <linux/tegra-fuse.h>
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#include "regops_gm20b.h"
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#define FUSE_OPT_PRIV_SEC_DIS_0 0x264
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#define PRIV_SECURITY_DISABLE 0x01
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struct gpu_ops gm20b_ops = {
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.clock_gating = {
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.slcg_bus_load_gating_prod =
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gm20b_slcg_bus_load_gating_prod,
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.slcg_ce2_load_gating_prod =
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gm20b_slcg_ce2_load_gating_prod,
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.slcg_chiplet_load_gating_prod =
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gm20b_slcg_chiplet_load_gating_prod,
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.slcg_ctxsw_firmware_load_gating_prod =
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gm20b_slcg_ctxsw_firmware_load_gating_prod,
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.slcg_fb_load_gating_prod =
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gm20b_slcg_fb_load_gating_prod,
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.slcg_fifo_load_gating_prod =
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gm20b_slcg_fifo_load_gating_prod,
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.slcg_gr_load_gating_prod =
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gr_gm20b_slcg_gr_load_gating_prod,
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.slcg_ltc_load_gating_prod =
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ltc_gm20b_slcg_ltc_load_gating_prod,
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.slcg_perf_load_gating_prod =
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gm20b_slcg_perf_load_gating_prod,
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.slcg_priring_load_gating_prod =
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gm20b_slcg_priring_load_gating_prod,
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.slcg_pmu_load_gating_prod =
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gm20b_slcg_pmu_load_gating_prod,
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.slcg_therm_load_gating_prod =
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gm20b_slcg_therm_load_gating_prod,
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.slcg_xbar_load_gating_prod =
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gm20b_slcg_xbar_load_gating_prod,
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.blcg_bus_load_gating_prod =
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gm20b_blcg_bus_load_gating_prod,
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.blcg_ctxsw_firmware_load_gating_prod =
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gm20b_blcg_ctxsw_firmware_load_gating_prod,
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.blcg_fb_load_gating_prod =
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gm20b_blcg_fb_load_gating_prod,
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.blcg_fifo_load_gating_prod =
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gm20b_blcg_fifo_load_gating_prod,
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.blcg_gr_load_gating_prod =
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gm20b_blcg_gr_load_gating_prod,
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.blcg_ltc_load_gating_prod =
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gm20b_blcg_ltc_load_gating_prod,
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.blcg_pwr_csb_load_gating_prod =
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gm20b_blcg_pwr_csb_load_gating_prod,
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.blcg_pmu_load_gating_prod =
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gm20b_blcg_pmu_load_gating_prod,
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.pg_gr_load_gating_prod =
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gr_gm20b_pg_gr_load_gating_prod,
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}
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};
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int gm20b_init_hal(struct gpu_ops *gops)
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{
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*gops = gm20b_ops;
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#ifdef CONFIG_TEGRA_ACR
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if (tegra_platform_is_linsim()) {
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gops->privsecurity = 1;
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} else {
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if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_DIS_0) &
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PRIV_SECURITY_DISABLE) {
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gk20a_dbg_info("priv security is disabled in HW");
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gops->privsecurity = 0;
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} else {
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gops->privsecurity = 1;
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}
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}
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#else
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if (tegra_platform_is_linsim()) {
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gk20a_dbg_info("running ASIM with PRIV security disabled");
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gops->privsecurity = 0;
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} else {
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if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_DIS_0) &
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PRIV_SECURITY_DISABLE) {
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gops->privsecurity = 0;
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} else {
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gk20a_dbg_info("priv security is not supported but enabled");
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gops->privsecurity = 1;
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return -EPERM;
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}
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}
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#endif
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gm20b_init_ltc(gops);
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gm20b_init_gr(gops);
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gm20b_init_ltc(gops);
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gm20b_init_fb(gops);
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gm20b_init_fifo(gops);
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gm20b_init_gr_ctx(gops);
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gm20b_init_mm(gops);
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gm20b_init_pmu_ops(gops);
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gm20b_init_clk_ops(gops);
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gm20b_init_regops(gops);
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gops->name = "gm20b";
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return 0;
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}
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