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a52a50d407
based on the config setting and fuse secure no non secure boot is done Change-Id: I5937ba945c5a3a86f72e0f2a9078fcde01977137 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/487684 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
159 lines
4.2 KiB
C
159 lines
4.2 KiB
C
/*
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* GM20B PMU
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*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "gk20a/gk20a.h"
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#include "acr_gm20b.h"
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#include "pmu_gm20b.h"
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/*!
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* Structure/object which single register write need to be done during PG init
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* sequence to set PROD values.
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*/
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struct pg_init_sequence_list {
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u32 regaddr;
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u32 writeval;
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};
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/* PROD settings for ELPG sequencing registers*/
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static struct pg_init_sequence_list _pginitseq_gm20b[] = {
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{ 0x0010ab10, 0x8180},
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{ 0x0010e118, 0x81818080},
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{ 0x0010e068, 0},
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{ 0x0010e06c, 0x00000080},
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{ 0x0010e06c, 0x00000080},
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{ 0x0010e06c, 0x00000081},
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{ 0x0010e06c, 0x00000081},
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{ 0x0010e06c, 0x00000082},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000080},
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{ 0x0010e06c, 0x00000080},
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{ 0x0010e06c, 0x00000081},
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{ 0x0010e06c, 0x00000081},
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{ 0x0010e06c, 0x00000082},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000080},
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{ 0x0010e06c, 0x00000080},
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{ 0x0010e06c, 0x00000081},
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{ 0x0010e06c, 0x00000081},
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{ 0x0010e06c, 0x00000082},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000080},
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{ 0x0010e06c, 0x00000080},
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{ 0x0010e06c, 0x00000081},
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{ 0x0010e06c, 0x00000081},
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{ 0x0010e06c, 0x00000082},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000080},
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{ 0x0010e06c, 0x00000080},
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{ 0x0010e06c, 0x00000081},
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{ 0x0010e06c, 0x00000081},
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{ 0x0010e06c, 0x00000082},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000080},
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{ 0x0010e06c, 0x00000080},
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{ 0x0010e06c, 0x00000081},
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{ 0x0010e06c, 0x00000081},
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{ 0x0010e06c, 0x00000082},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010e06c, 0x00000080},
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{ 0x0010e06c, 0x00000080},
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{ 0x0010e06c, 0x00000081},
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{ 0x0010e06c, 0x00000081},
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{ 0x0010e06c, 0x00000082},
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{ 0x0010e06c, 0x00000083},
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{ 0x0010ab14, 0x00000000},
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{ 0x0010ab18, 0x00000000},
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{ 0x0010e024, 0x00000000},
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{ 0x0010e028, 0x00000000},
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{ 0x0010e11c, 0x00000000},
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{ 0x0010e120, 0x00000000},
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{ 0x0010ab1c, 0x00010011},
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{ 0x0010e020, 0x001C0011},
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{ 0x0010e124, 0x00030011},
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{ 0x0010ab20, 0xfedcba98},
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{ 0x0010ab24, 0x00000000},
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{ 0x0010e02c, 0xfedcba98},
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{ 0x0010e030, 0x00000000},
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{ 0x0010e128, 0xfedcba98},
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{ 0x0010e12c, 0x00000000},
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{ 0x0010ab28, 0x71111111},
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{ 0x0010ab2c, 0x70000000},
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{ 0x0010e034, 0x71111111},
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{ 0x0010e038, 0x70000000},
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{ 0x0010e130, 0x71111111},
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{ 0x0010e134, 0x70000000},
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{ 0x0010ab30, 0x00000000},
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{ 0x0010ab34, 0x00000001},
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{ 0x00020004, 0x00000000},
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{ 0x0010e138, 0x00000000},
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{ 0x0010e040, 0x00000000},
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};
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int gm20b_pmu_setup_elpg(struct gk20a *g)
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{
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int ret = 0;
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u32 reg_writes;
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u32 index;
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gk20a_dbg_fn("");
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if (g->elpg_enabled) {
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reg_writes = ((sizeof(_pginitseq_gm20b) /
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sizeof((_pginitseq_gm20b)[0])));
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/* Initialize registers with production values*/
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for (index = 0; index < reg_writes; index++) {
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gk20a_writel(g, _pginitseq_gm20b[index].regaddr,
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_pginitseq_gm20b[index].writeval);
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}
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}
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gk20a_dbg_fn("done");
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return ret;
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}
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void gm20b_init_pmu_ops(struct gpu_ops *gops)
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{
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if (gops->privsecurity)
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gm20b_init_secure_pmu(gops);
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else
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gk20a_init_pmu_ops(gops);
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gops->pmu.pmu_setup_elpg = gm20b_pmu_setup_elpg;
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}
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