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61b263d832
Replace existing usages of wait_queue_head_t with struct nvgpu_cond and using the corresponding APIs in order to reduce Linux dependencies in NVGPU. JIRA NVGPU-205 Change-Id: I85850369c3c47d3e1704e4171b1d172361842423 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1575778 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
75 lines
2.3 KiB
C
75 lines
2.3 KiB
C
/*
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* general p state infrastructure
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*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __PSTATE_H__
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#define __PSTATE_H__
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#include "clk/clk.h"
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#define CTRL_PERF_PSTATE_TYPE_3X 0x3
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#define CTRL_PERF_PSTATE_P0 0
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#define CTRL_PERF_PSTATE_P5 5
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#define CTRL_PERF_PSTATE_P8 8
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#define CLK_SET_INFO_MAX_SIZE (32)
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struct gk20a;
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struct clk_set_info {
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enum nv_pmu_clk_clkwhich clkwhich;
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u32 nominal_mhz;
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u32 min_mhz;
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u32 max_mhz;
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};
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struct clk_set_info_list {
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u32 num_info;
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struct clk_set_info clksetinfo[CLK_SET_INFO_MAX_SIZE];
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};
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struct pstate {
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struct boardobj super;
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u32 num;
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u8 lpwr_entry_idx;
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struct clk_set_info_list clklist;
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};
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struct pstates {
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struct boardobjgrp_e32 super;
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u32 num_levels;
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struct nvgpu_cond pstate_notifier_wq;
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u32 is_pstate_switch_on;
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struct nvgpu_mutex pstate_mutex; /* protect is_pstate_switch_on */
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};
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int gk20a_init_pstate_support(struct gk20a *g);
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void gk20a_deinit_pstate_support(struct gk20a *g);
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int gk20a_init_pstate_pmu_support(struct gk20a *g);
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struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, u32 pstate_num,
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enum nv_pmu_clk_clkwhich clkwhich);
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struct pstate *pstate_find(struct gk20a *g, u32 num);
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#endif /* __PSTATE_H__ */
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