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6eae6df6da
Bootstrapping LS falcons is done by SEC2 by sending commands to SEC2 RTOS. This requires interaction with SEC2 cmd and msg units. Hence prepare separate unit. JIRA NVGPU-2074 Change-Id: I5a27b4eef3fa3f11bcaac8bd9494fe771b921cf9 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2085750 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
112 lines
2.8 KiB
C
112 lines
2.8 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/log.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/sec2.h>
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#include <nvgpu/sec2/queue.h>
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#include <nvgpu/sec2/seq.h>
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#include <nvgpu/sec2if/sec2_if_cmn.h>
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#include <nvgpu/sec2/allocator.h>
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#include <nvgpu/sec2/msg.h>
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static void nvgpu_remove_sec2_support(struct nvgpu_sec2 *sec2)
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{
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struct gk20a *g = sec2->g;
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nvgpu_log_fn(g, " ");
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nvgpu_sec2_sequences_free(g, &sec2->sequences);
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nvgpu_mutex_destroy(&sec2->isr_mutex);
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}
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int nvgpu_init_sec2_setup_sw(struct gk20a *g, struct nvgpu_sec2 *sec2)
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{
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int err = 0;
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nvgpu_log_fn(g, " ");
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sec2->g = g;
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err = nvgpu_sec2_sequences_alloc(g, &sec2->sequences);
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if (err != 0) {
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goto exit;
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}
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nvgpu_sec2_sequences_init(g, &sec2->sequences);
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err = nvgpu_mutex_init(&sec2->isr_mutex);
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if (err != 0) {
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goto free_sequences;
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}
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sec2->remove_support = nvgpu_remove_sec2_support;
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goto exit;
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free_sequences:
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nvgpu_sec2_sequences_free(g, &sec2->sequences);
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exit:
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return err;
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}
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int nvgpu_init_sec2_support(struct gk20a *g)
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{
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struct nvgpu_sec2 *sec2 = &g->sec2;
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int err = 0;
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nvgpu_log_fn(g, " ");
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/* Enable irq*/
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nvgpu_mutex_acquire(&sec2->isr_mutex);
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g->ops.sec2.enable_irq(sec2, true);
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sec2->isr_enabled = true;
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nvgpu_mutex_release(&sec2->isr_mutex);
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/* execute SEC2 in secure mode to boot RTOS */
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g->ops.sec2.secured_sec2_start(g);
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return err;
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}
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int nvgpu_sec2_destroy(struct gk20a *g)
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{
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struct nvgpu_sec2 *sec2 = &g->sec2;
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nvgpu_log_fn(g, " ");
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nvgpu_sec2_dmem_allocator_destroy(&sec2->dmem);
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nvgpu_mutex_acquire(&sec2->isr_mutex);
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sec2->isr_enabled = false;
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nvgpu_mutex_release(&sec2->isr_mutex);
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nvgpu_sec2_queues_free(g, sec2->queues);
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sec2->sec2_ready = false;
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return 0;
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}
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