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8c04d2f000
Currently, we are performing obj ctx alloction for bellow classes 1. VOLTA_COMPUTE_A 2. VOLTA_DMA_COPY_A 3. VOLTA_CHANNEL_GPFIFO_A In safety, we use Async CE but not GRCE. So allocating obj context only for COMPUTE_A and return success(0) for all other valid classes, after setting class in the channel struct. Jira NVGPU-4378 Change-Id: Ie99872e062cc66f9ddf699397a13df85c3d8d59e Signed-off-by: sagar <skadamati@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287486 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
73 lines
2.0 KiB
C
73 lines
2.0 KiB
C
/*
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* Copyright (c) 2019 NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/class.h>
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#include <nvgpu/barrier.h>
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#include "class_gm20b.h"
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#include "class_gp10b.h"
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bool gp10b_class_is_valid(u32 class_num)
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{
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bool valid;
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nvgpu_speculation_barrier();
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switch (class_num) {
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case PASCAL_DMA_COPY_A:
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case PASCAL_CHANNEL_GPFIFO_A:
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valid = true;
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break;
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#ifdef CONFIG_NVGPU_GRAPHICS
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case PASCAL_A:
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valid = true;
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break;
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#endif
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case PASCAL_COMPUTE_A:
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valid = true;
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break;
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default:
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valid = gm20b_class_is_valid(class_num);
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break;
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}
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return valid;
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}
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#ifdef CONFIG_NVGPU_GRAPHICS
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bool gp10b_class_is_valid_gfx(u32 class_num)
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{
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if (class_num == PASCAL_A || class_num == MAXWELL_B) {
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return true;
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} else {
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return false;
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}
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}
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#endif
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bool gp10b_class_is_valid_compute(u32 class_num)
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{
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if (class_num == PASCAL_COMPUTE_A || class_num == MAXWELL_COMPUTE_B) {
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return true;
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} else {
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return false;
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}
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}
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