mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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2a865e3aad
This patch adds nvenc support for TU104 - Fetch engine/dev info for nvenc - Falcon NS boot (fw loading) support - Engine context creation for nvenc - Skip golden image for multimedia engines - Avoid subctx for nvenc as it is a non-VEID engine - Job submission/flow changes for nvenc - Code refactoring to scale up the support for other multimedia engines in future. Bug 3763551 Change-Id: I03d4e731ebcef456bcc5ce157f3aa39883270dc0 Signed-off-by: Santosh BS <santoshb@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859416 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
122 lines
3.6 KiB
C
122 lines
3.6 KiB
C
/*
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* Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/channel.h>
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#include <nvgpu/log.h>
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#include <nvgpu/atomic.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/runlist.h>
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#include "channel_gk20a.h"
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#include "channel_gv11b.h"
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#include <nvgpu/hw/gv11b/hw_ccsr_gv11b.h>
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void gv11b_channel_bind(struct nvgpu_channel *ch)
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{
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struct gk20a *g = ch->g;
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int err;
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u32 inst_ptr = nvgpu_inst_block_ptr(g, &ch->inst_block);
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nvgpu_log_info(g, "bind channel %d inst ptr 0x%08x",
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ch->chid, inst_ptr);
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/* Enable subcontext */
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if ((g->ops.tsg.add_subctx_channel_hw != NULL) &&
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(!nvgpu_engine_is_multimedia_runlist_id(g, ch->runlist->id))) {
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err = g->ops.tsg.add_subctx_channel_hw(ch, ch->replayable);
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if (err != 0) {
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nvgpu_err(g, "Subcontext addition failed %d", err);
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return;
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}
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}
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/* Enable channel */
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nvgpu_writel(g, ccsr_channel_inst_r(ch->chid),
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ccsr_channel_inst_ptr_f(inst_ptr) |
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nvgpu_aperture_mask(g, &ch->inst_block,
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ccsr_channel_inst_target_sys_mem_ncoh_f(),
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ccsr_channel_inst_target_sys_mem_coh_f(),
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ccsr_channel_inst_target_vid_mem_f()) |
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ccsr_channel_inst_bind_true_f());
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nvgpu_writel(g, ccsr_channel_r(ch->chid),
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(nvgpu_readl(g, ccsr_channel_r(ch->chid)) &
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~ccsr_channel_enable_set_f(~U32(0U))) |
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ccsr_channel_enable_set_true_f());
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nvgpu_atomic_set(&ch->bound, 1);
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}
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void gv11b_channel_unbind(struct nvgpu_channel *ch)
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{
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struct gk20a *g = ch->g;
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nvgpu_log_fn(g, " ");
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if (nvgpu_atomic_cmpxchg(&ch->bound, 1, 0) != 0) {
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nvgpu_writel(g, ccsr_channel_inst_r(ch->chid),
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ccsr_channel_inst_ptr_f(0U) |
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ccsr_channel_inst_bind_false_f());
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nvgpu_writel(g, ccsr_channel_r(ch->chid),
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ccsr_channel_enable_clr_true_f() |
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ccsr_channel_pbdma_faulted_reset_f() |
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ccsr_channel_eng_faulted_reset_f());
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}
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}
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u32 gv11b_channel_count(struct gk20a *g)
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{
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(void)g;
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return ccsr_channel__size_1_v();
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}
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void gv11b_channel_read_state(struct gk20a *g, u32 runlist_id, u32 chid,
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struct nvgpu_channel_hw_state *state)
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{
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u32 reg = nvgpu_readl(g, ccsr_channel_r(chid));
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gk20a_channel_read_state(g, runlist_id, chid, state);
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state->eng_faulted = ccsr_channel_eng_faulted_v(reg) ==
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ccsr_channel_eng_faulted_true_v();
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}
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void gv11b_channel_reset_faulted(struct gk20a *g, struct nvgpu_channel *ch,
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bool eng, bool pbdma)
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{
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u32 reg = nvgpu_readl(g, ccsr_channel_r(ch->chid));
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if (eng) {
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reg |= ccsr_channel_eng_faulted_reset_f();
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}
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if (pbdma) {
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reg |= ccsr_channel_pbdma_faulted_reset_f();
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}
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nvgpu_writel(g, ccsr_channel_r(ch->chid), reg);
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}
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