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9feb9ea742
When profiler session is terminated abnormally, PMA control path is still in active/incorrect state with existing teardown sequence. This change ensures we clear PMA command slice registers before we wait for routers to be idle. Once PMM routers are idle, we clear PMA channel registers to drain all the in-flight records. Bug 4123716 Change-Id: I0659dc89b00f468c2f2df5af952ac68c70387746 Signed-off-by: Kishan <kpalankar@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com> (cherry picked from commit 64bcf057bf0930f414a700a378d33ee098bdf2e2) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2973882 Reviewed-by: Ramalingam C <ramalingamc@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
79 lines
3.4 KiB
C
79 lines
3.4 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2020-2023, NVIDIA CORPORATION & AFFILIATES.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GA10B_PERF
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#define NVGPU_GA10B_PERF
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#ifdef CONFIG_NVGPU_DEBUGGER
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_mem;
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bool ga10b_perf_get_membuf_overflow_status(struct gk20a *g);
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u32 ga10b_perf_get_membuf_pending_bytes(struct gk20a *g);
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void ga10b_perf_set_membuf_handled_bytes(struct gk20a *g,
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u32 entries, u32 entry_size);
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void ga10b_perf_membuf_reset_streaming(struct gk20a *g);
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void ga10b_perf_enable_membuf(struct gk20a *g, u32 size, u64 buf_addr);
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void ga10b_perf_disable_membuf(struct gk20a *g);
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void ga10b_perf_bind_mem_bytes_buffer_addr(struct gk20a *g, u64 buf_addr);
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void ga10b_perf_init_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block);
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void ga10b_perf_deinit_inst_block(struct gk20a *g);
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u32 ga10b_perf_get_pmmsys_per_chiplet_offset(void);
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u32 ga10b_perf_get_pmmgpc_per_chiplet_offset(void);
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u32 ga10b_perf_get_pmmfbp_per_chiplet_offset(void);
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u32 ga10b_perf_get_pmmgpcrouter_per_chiplet_offset(void);
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u32 ga10b_perf_get_pmmfbprouter_per_chiplet_offset(void);
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const u32 *ga10b_perf_get_hwpm_sys_perfmon_regs(u32 *count);
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const u32 *ga10b_perf_get_hwpm_gpc_perfmon_regs(u32 *count);
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const u32 *ga10b_perf_get_hwpm_fbp_perfmon_regs(u32 *count);
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u32 ga10b_get_hwpm_fbp_perfmon_regs_base(struct gk20a *g);
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u32 ga10b_get_hwpm_gpc_perfmon_regs_base(struct gk20a *g);
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void ga10b_perf_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon,
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u32 *num_fbp_perfmon, u32 *num_gpc_perfmon);
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void ga10b_perf_init_hwpm_pmm_register(struct gk20a *g);
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void ga10b_perf_disable_all_perfmons(struct gk20a *g);
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void ga10b_perf_pma_stream_enable(struct gk20a *g, bool enable);
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int ga10b_perf_wait_for_idle_pma(struct gk20a *g);
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int ga10b_perf_update_get_put(struct gk20a *g, u64 bytes_consumed,
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bool update_available_bytes, u64 *put_ptr, bool *overflowed);
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void ga10b_perf_enable_hs_streaming(struct gk20a *g, bool enable);
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void ga10b_perf_reset_hs_streaming_credits(struct gk20a *g);
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void ga10b_perf_enable_pmasys_legacy_mode(struct gk20a *g, bool enable);
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void ga10b_perf_reset_hwpm_pma_registers(struct gk20a *g);
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void ga10b_perf_reset_hwpm_pma_trigger_registers(struct gk20a *g);
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void ga10b_perf_reset_pmasys_channel_registers(struct gk20a *g);
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#endif /* CONFIG_NVGPU_DEBUGGER */
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#endif
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