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26b90cc6f3
The nvgpu_gr_zcull struct need not be part of public zcull header. Move it to a common.gr unit header and update gr/hal users. JIRA NVGPU-3060 Change-Id: I5c821f98ab304c5486b4a2630ac5827f1203dae7 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2084806 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
46 lines
1.5 KiB
C
46 lines
1.5 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_ZCULL_PRIV_H
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#define NVGPU_GR_ZCULL_PRIV_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_gr_zcull {
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struct gk20a *g;
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u32 aliquot_width;
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u32 aliquot_height;
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u32 aliquot_size;
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u32 total_aliquots;
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u32 width_align_pixels;
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u32 height_align_pixels;
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u32 pixel_squares_by_aliquots;
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u32 zcull_ctxsw_image_size;
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};
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#endif /* NVGPU_GR_ZCULL_PRIV_H */
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