Seema Khowala 6f6329c377 gpu: nvgpu: gv11b: init set_hww_esr_report_mask ...

gv11b has 2 SMs per TPC. Use *gpcs_tpcs_sms_hww_warp/global_esr*
registers instead of *gpcs_tpcs_sm_hww_warp/global_esr*

GPUT19X-75

Change-Id: I86c7ded32b2b69214e047e6de67a1745f2cef6f3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1474860
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

2017-06-30 00:05:05 -07:00

..

nvgpu

gpu: nvgpu: gv11b: init set_hww_esr_report_mask

2017-06-30 00:05:05 -07:00