mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-24 02:22:34 +03:00
f6c96f620f
The following functions belong to the path of kernel_mode submit and the flag CONFIG_NVGPU_KERNEL_MODE_SUBMIT is used to compile these out of safety builds. channel_gk20a_alloc_priv_cmdbuf channel_gk20a_free_prealloc_resources channel_gk20a_joblist_add channel_gk20a_joblist_delete channel_gk20a_joblist_peek channel_gk20a_prealloc_resources nvgpu_channel nvgpu_channel_add_job nvgpu_channel_alloc_job nvgpu_channel_alloc_priv_cmdbuf nvgpu_channel_clean_up_jobs nvgpu_channel_free_job nvgpu_channel_free_priv_cmd_entry nvgpu_channel_free_priv_cmd_q nvgpu_channel_from_worker_item nvgpu_channel_get_gpfifo_free_count nvgpu_channel_is_prealloc_enabled nvgpu_channel_joblist_is_empty nvgpu_channel_joblist_lock nvgpu_channel_joblist_unlock nvgpu_channel_kernelmode_deinit nvgpu_channel_poll_wdt nvgpu_channel_set_syncpt nvgpu_channel_setup_kernelmode nvgpu_channel_sync_get_ref nvgpu_channel_sync_incr nvgpu_channel_sync_incr_user nvgpu_channel_sync_put_ref_and_check nvgpu_channel_sync_wait_fence_fd nvgpu_channel_update nvgpu_channel_update_gpfifo_get_and_get_free_count nvgpu_channel_update_priv_cmd_q_and_free_entry nvgpu_channel_wdt_continue nvgpu_channel_wdt_handler nvgpu_channel_wdt_init nvgpu_channel_wdt_restart_all_channels nvgpu_channel_wdt_restart_all_channels nvgpu_channel_wdt_rewind nvgpu_channel_wdt_start nvgpu_channel_wdt_stop nvgpu_channel_worker_deinit nvgpu_channel_worker_from_worker nvgpu_channel_worker_init nvgpu_channel_worker_poll_init nvgpu_channel_worker_poll_wakeup_post_process_item nvgpu_channel_worker_poll_wakeup_process_item nvgpu_submit_channel_gpfifo_kernel nvgpu_submit_channel_gpfifo_user gk20a_userd_gp_get gk20a_userd_pb_get gk20a_userd_gp_put nvgpu_fence_alloc The following members of struct nvgpu_channel are compiled out of safety build. struct gpfifo_desc gpfifo; struct priv_cmd_queue priv_cmd_q; struct nvgpu_channel_sync *sync; struct nvgpu_list_node worker_item; struct nvgpu_channel_wdt wdt; The following files are compiled out of safety build. common/fifo/submit.c common/sync/channe1_sync_semaphore.c hal/fifo/userd_gv11b.c Jira NVGPU-3479 Change-Id: If46c936477c6698f4bec3cab93906aaacb0ceabf Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2127212 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
92 lines
3.1 KiB
C
92 lines
3.1 KiB
C
/*
|
|
* GK20A USERD
|
|
*
|
|
* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
* DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include <nvgpu/bug.h>
|
|
#include <nvgpu/channel.h>
|
|
#include <nvgpu/gk20a.h>
|
|
#include <nvgpu/io.h>
|
|
#include <nvgpu/nvgpu_mem.h>
|
|
|
|
#include "userd_gk20a.h"
|
|
|
|
#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
|
|
|
|
void gk20a_userd_init_mem(struct gk20a *g, struct nvgpu_channel *c)
|
|
{
|
|
struct nvgpu_mem *mem = c->userd_mem;
|
|
u32 offset = c->userd_offset / U32(sizeof(u32));
|
|
|
|
nvgpu_log_fn(g, " ");
|
|
|
|
nvgpu_mem_wr32(g, mem, offset + ram_userd_put_w(), 0);
|
|
nvgpu_mem_wr32(g, mem, offset + ram_userd_get_w(), 0);
|
|
nvgpu_mem_wr32(g, mem, offset + ram_userd_ref_w(), 0);
|
|
nvgpu_mem_wr32(g, mem, offset + ram_userd_put_hi_w(), 0);
|
|
nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_top_level_get_w(), 0);
|
|
nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_top_level_get_hi_w(), 0);
|
|
nvgpu_mem_wr32(g, mem, offset + ram_userd_get_hi_w(), 0);
|
|
nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_get_w(), 0);
|
|
nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_put_w(), 0);
|
|
}
|
|
|
|
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
|
|
u32 gk20a_userd_gp_get(struct gk20a *g, struct nvgpu_channel *c)
|
|
{
|
|
u64 userd_gpu_va = nvgpu_channel_userd_gpu_va(c);
|
|
u64 addr = userd_gpu_va + sizeof(u32) * ram_userd_gp_get_w();
|
|
|
|
BUG_ON(u64_hi32(addr) != 0U);
|
|
|
|
return nvgpu_bar1_readl(g, (u32)addr);
|
|
}
|
|
|
|
u64 gk20a_userd_pb_get(struct gk20a *g, struct nvgpu_channel *c)
|
|
{
|
|
u64 userd_gpu_va = nvgpu_channel_userd_gpu_va(c);
|
|
u64 lo_addr = userd_gpu_va + sizeof(u32) * ram_userd_get_w();
|
|
u64 hi_addr = userd_gpu_va + sizeof(u32) * ram_userd_get_hi_w();
|
|
u32 lo, hi;
|
|
|
|
BUG_ON((u64_hi32(lo_addr) != 0U) || (u64_hi32(hi_addr) != 0U));
|
|
lo = nvgpu_bar1_readl(g, (u32)lo_addr);
|
|
hi = nvgpu_bar1_readl(g, (u32)hi_addr);
|
|
|
|
return ((u64)hi << 32) | lo;
|
|
}
|
|
|
|
void gk20a_userd_gp_put(struct gk20a *g, struct nvgpu_channel *c)
|
|
{
|
|
u64 userd_gpu_va = nvgpu_channel_userd_gpu_va(c);
|
|
u64 addr = userd_gpu_va + sizeof(u32) * ram_userd_gp_put_w();
|
|
|
|
BUG_ON(u64_hi32(addr) != 0U);
|
|
nvgpu_bar1_writel(g, (u32)addr, c->gpfifo.put);
|
|
}
|
|
#endif
|
|
|
|
u32 gk20a_userd_entry_size(struct gk20a *g)
|
|
{
|
|
return BIT32(ram_userd_base_shift_v());
|
|
}
|