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Following are removed for safety build by adding CONFIG_NVGPU_KERNEL_MODE_SUBMIT flag. 1) HAL ops in g->ops.sync.syncpt add_wait_cmd get_wait_cmd_size add_incr_cmd get_incr_cmd_size get_incr_per_release 2) g->ops.sync.sema is removed in its entirety and contains the following ops. 3) The following files are compiled out using the above flag. hal/sync/sema_cmdbuf_gk20a.c hal/sync/sema_cmdbuf_gv11b.c Jira NVGPU-3479 Change-Id: I99ae6913e5fe5707ff9a3e2cf06cee8710def7cc Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2130352 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
90 lines
2.7 KiB
C
90 lines
2.7 KiB
C
/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_SYNC_SYNCPT_CMDBUF_GK20A_H
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#define NVGPU_SYNC_SYNCPT_CMDBUF_GK20A_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct priv_cmd_entry;
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struct nvgpu_mem;
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#ifdef CONFIG_TEGRA_GK20A_NVHOST
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#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
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void gk20a_syncpt_add_wait_cmd(struct gk20a *g,
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struct priv_cmd_entry *cmd, u32 off,
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u32 id, u32 thresh, u64 gpu_va);
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u32 gk20a_syncpt_get_wait_cmd_size(void);
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u32 gk20a_syncpt_get_incr_per_release(void);
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void gk20a_syncpt_add_incr_cmd(struct gk20a *g,
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bool wfi_cmd, struct priv_cmd_entry *cmd,
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u32 id, u64 gpu_va);
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u32 gk20a_syncpt_get_incr_cmd_size(bool wfi_cmd);
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#endif
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void gk20a_syncpt_free_buf(struct nvgpu_channel *c,
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struct nvgpu_mem *syncpt_buf);
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int gk20a_syncpt_alloc_buf(struct nvgpu_channel *c,
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u32 syncpt_id, struct nvgpu_mem *syncpt_buf);
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#else
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#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
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static inline void gk20a_syncpt_add_wait_cmd(struct gk20a *g,
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struct priv_cmd_entry *cmd, u32 off,
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u32 id, u32 thresh, u64 gpu_va)
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{
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}
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static inline u32 gk20a_syncpt_get_wait_cmd_size(void)
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{
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return 0U;
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}
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static inline u32 gk20a_syncpt_get_incr_per_release(void)
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{
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return 0U;
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}
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static inline void gk20a_syncpt_add_incr_cmd(struct gk20a *g,
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bool wfi_cmd, struct priv_cmd_entry *cmd,
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u32 id, u64 gpu_va)
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{
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}
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static inline u32 gk20a_syncpt_get_incr_cmd_size(bool wfi_cmd)
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{
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return 0U;
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}
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#endif
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static inline void gk20a_syncpt_free_buf(struct nvgpu_channel *c,
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struct nvgpu_mem *syncpt_buf)
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{
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}
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static inline int gk20a_syncpt_alloc_buf(struct nvgpu_channel *c,
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u32 syncpt_id, struct nvgpu_mem *syncpt_buf)
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{
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return -ENOSYS;
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}
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#endif
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#endif /* NVGPU_SYNC_SYNCPT_CMDBUF_GK20A_H */ |