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ad3cf4e79a
Disabled graphics class support for safety build. JIRA NVGPU-4314 Change-Id: I72ea732263f1777cb19fffa0c0128deeb435efa6 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2233581 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
108 lines
3.0 KiB
C
108 lines
3.0 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CLASS_H
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#define NVGPU_CLASS_H
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/**
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* @defgroup NVGPU_CLASS_VALID_NUM
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*
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* List of valid class numbers allowed in FuSa code.
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*/
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/**
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* @ingroup NVGPU_CLASS_VALID_NUM
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*
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* Class number for DMA copy class methods on Kepler chips.
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*/
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#define KEPLER_DMA_COPY_A 0xA0B5U
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/**
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* @ingroup NVGPU_CLASS_VALID_NUM
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*
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* Class number for Inline to memory class methods on Kepler and chips beyond.
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* The source data is always from the pushbuffer, hence the name
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* inline_to_memory.
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*/
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#define KEPLER_INLINE_TO_MEMORY_B 0xA140U
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/**
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* @ingroup NVGPU_CLASS_VALID_NUM
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*
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* Class number for Channel_GPFIFO class methods on Maxwell chips.
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*/
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#define MAXWELL_CHANNEL_GPFIFO_A 0xB06FU
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/**
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* @ingroup NVGPU_CLASS_VALID_NUM
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*
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* Class number for DMA copy class methods on Maxwell chips.
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*/
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#define MAXWELL_DMA_COPY_A 0xB0B5U
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/**
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* @ingroup NVGPU_CLASS_VALID_NUM
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*
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* Class number for Channel_GPFIFO class methods on Pascal chips.
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*/
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#define PASCAL_CHANNEL_GPFIFO_A 0xC06FU
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/**
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* @ingroup NVGPU_CLASS_VALID_NUM
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*
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* Class number for DMA copy class methods on Pascal chips.
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*/
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#define PASCAL_DMA_COPY_A 0xC0B5U
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/**
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* @ingroup NVGPU_CLASS_VALID_NUM
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*
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* Class number for Channel_GPFIFO class methods on Volta chips.
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*/
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#define VOLTA_CHANNEL_GPFIFO_A 0xC36FU
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/**
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* @ingroup NVGPU_CLASS_VALID_NUM
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*
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* Class number for compute class methods on Volta chips.
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*/
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#define VOLTA_COMPUTE_A 0xC3C0U
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/**
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* @ingroup NVGPU_CLASS_VALID_NUM
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*
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* Class number for DMA copy class methods on Volta chips.
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*/
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#define VOLTA_DMA_COPY_A 0xC3B5U
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#ifdef CONFIG_NVGPU_GRAPHICS
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#define FERMI_TWOD_A 0x902DU
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#define MAXWELL_B 0xB197U
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#define PASCAL_A 0xC097U
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#define VOLTA_A 0xC397U
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#define TURING_A 0xC597U
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#endif
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#ifdef CONFIG_NVGPU_NON_FUSA
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#define MAXWELL_COMPUTE_B 0xB1C0U
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#define PASCAL_COMPUTE_A 0xC0C0U
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#define TURING_CHANNEL_GPFIFO_A 0xC46FU
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#define TURING_COMPUTE_A 0xC5C0U
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#define TURING_DMA_COPY_A 0xC5B5U
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#endif
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#endif /* NVGPU_CLASS_H */
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