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b33079d47e
Move interrupt specific data-members from common.mc to common.cic Some of these data members like sw_irq_stall_last_handled_cond need To be initialized much earlier during the OS specific init/probe stage. Also, some more members from struct nvgpu_interrupts(like stall_size, stall_lines[]), which will soon be moved to CIC will also need to be initialized early during the OS specific probe stage. However, the chip specific LUT can only be initialized after the hal_init stage where the HALs are all initialized. Split the CIC init to accommodate the above initialization requirements. JIRA NVGPU-6899 Change-Id: I9333db4cde59bb0aa8f6eb9f8472f00369817a5d Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2552535 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
107 lines
3.0 KiB
C
107 lines
3.0 KiB
C
/*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/cic_rm.h>
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#include <nvgpu/gk20a.h>
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#include "cic_rm_priv.h"
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void nvgpu_cic_rm_set_irq_stall(struct gk20a *g, u32 value)
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{
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nvgpu_atomic_set(&g->cic_rm->sw_irq_stall_pending, value);
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}
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void nvgpu_cic_rm_set_irq_nonstall(struct gk20a *g, u32 value)
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{
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nvgpu_atomic_set(&g->cic_rm->sw_irq_nonstall_pending, value);
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}
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int nvgpu_cic_rm_broadcast_last_irq_stall(struct gk20a *g)
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{
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int err = 0;
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err = nvgpu_cond_broadcast(
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&g->cic_rm->sw_irq_stall_last_handled_cond);
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if (err != 0) {
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nvgpu_err(g,
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"Last IRQ stall cond_broadcast failed err=%d",
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err);
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}
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return err;
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}
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int nvgpu_cic_rm_broadcast_last_irq_nonstall(struct gk20a *g)
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{
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int err = 0;
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err = nvgpu_cond_broadcast(
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&g->cic_rm->sw_irq_nonstall_last_handled_cond);
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if (err != 0) {
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nvgpu_err(g,
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"Last IRQ nonstall cond_broadcast failed err=%d",
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err);
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}
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return err;
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}
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int nvgpu_cic_rm_wait_for_stall_interrupts(struct gk20a *g, u32 timeout)
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{
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/* wait until all stalling irqs are handled */
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return NVGPU_COND_WAIT(&g->cic_rm->sw_irq_stall_last_handled_cond,
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nvgpu_atomic_read(&g->cic_rm->sw_irq_stall_pending) == 0,
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timeout);
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}
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int nvgpu_cic_rm_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout)
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{
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/* wait until all non-stalling irqs are handled */
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return NVGPU_COND_WAIT(&g->cic_rm->sw_irq_nonstall_last_handled_cond,
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nvgpu_atomic_read(&g->cic_rm->sw_irq_nonstall_pending) == 0,
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timeout);
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}
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void nvgpu_cic_rm_wait_for_deferred_interrupts(struct gk20a *g)
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{
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int ret;
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ret = nvgpu_cic_rm_wait_for_stall_interrupts(g, 0U);
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if (ret != 0) {
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nvgpu_err(g, "wait for stall interrupts failed %d", ret);
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}
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ret = nvgpu_cic_rm_wait_for_nonstall_interrupts(g, 0U);
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if (ret != 0) {
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nvgpu_err(g, "wait for nonstall interrupts failed %d", ret);
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}
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}
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#ifdef CONFIG_NVGPU_NON_FUSA
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void nvgpu_cic_rm_log_pending_intrs(struct gk20a *g)
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{
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if (g->ops.mc.log_pending_intrs != NULL) {
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g->ops.mc.log_pending_intrs(g);
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}
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}
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#endif
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