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700bd83b41
-Removed unwanded boardobj includes -Renamed functions as struct as per usage NVGPU-4484 Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com> Change-Id: I792a4b64075d5e87f911c1073717dbe7107227a1 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335991 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
85 lines
2.9 KiB
C
85 lines
2.9 KiB
C
/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CLK_H
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#define NVGPU_CLK_H
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#include <nvgpu/boardobjgrp_e255.h>
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#include "ucode_clk_inf.h"
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#define CTRL_CLK_FLL_REGIME_ID_INVALID ((u8)0x00000000)
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#define CTRL_CLK_FLL_REGIME_ID_FFR ((u8)0x00000001)
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#define CTRL_CLK_FLL_REGIME_ID_FR ((u8)0x00000002)
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#define CTRL_CLK_FLL_LUT_VSELECT_LOGIC (0x00000000U)
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#define CTRL_CLK_FLL_LUT_VSELECT_MIN (0x00000001U)
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#define CTRL_CLK_FLL_LUT_VSELECT_SRAM (0x00000002U)
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#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_HW_REQ (0x00000000U)
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#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_MIN (0x00000001U)
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#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_SW_REQ (0x00000003U)
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#define CTRL_CLK_VIN_STEP_SIZE_UV (6250U)
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#define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000U)
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#define CTRL_CLK_FLL_TYPE_DISABLED (0U)
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struct nvgpu_clk_pmupstate {
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struct nvgpu_avfsvinobjs *avfs_vinobjs;
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struct clk_avfs_fll_objs *avfs_fllobjs;
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struct nvgpu_clk_domains *clk_domainobjs;
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struct nvgpu_clk_progs *clk_progobjs;
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struct nvgpu_clk_vf_points *clk_vf_pointobjs;
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};
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struct clk_vf_point {
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struct pmu_board_obj super;
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u8 vfe_equ_idx;
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u8 volt_rail_idx;
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struct ctrl_clk_vf_pair pair;
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};
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struct clk_vf_point_volt {
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struct clk_vf_point super;
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u32 source_voltage_uv;
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struct ctrl_clk_freq_delta freq_delta;
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};
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struct clk_vf_point_freq {
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struct clk_vf_point super;
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int volt_delta_uv;
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};
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struct nvgpu_clk_vf_points {
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struct boardobjgrp_e255 super;
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};
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struct clk_vf_point *nvgpu_construct_clk_vf_point(struct gk20a *g,
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void *pargs);
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u32 nvgpu_pmu_clk_fll_get_lut_min_volt(struct nvgpu_clk_pmupstate *pclk);
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u8 clk_get_fll_lut_vf_num_entries(struct nvgpu_clk_pmupstate *pclk);
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struct clk_vin_device *clk_get_vin_from_index(
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struct nvgpu_avfsvinobjs *pvinobjs, u8 idx);
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int clk_domain_clk_prog_link(struct gk20a *g,
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struct nvgpu_clk_pmupstate *pclk);
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#endif /* NVGPU_CLK_VIN_H */
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