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git://nv-tegra.nvidia.com/linux-nvgpu.git
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cfc1281223
gp10b vgpu won't be supported on future releases. - removed gp10b vgpu hal code - removed vgpu bar1 related code - removed gp10b vgpu linux platform code Jira GVSCI-10202 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Change-Id: Ic1bfeb12c854df3808a0c7e67f5c52bc1e80ab2d Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2517273 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
137 lines
3.4 KiB
C
137 lines
3.4 KiB
C
/*
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* Virtualized GPU Fifo
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*
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* Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/trace.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/atomic.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/barrier.h>
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#include <nvgpu/io.h>
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#include <nvgpu/error_notifier.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/runlist.h>
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#include <nvgpu/string.h>
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#include <nvgpu/vm_area.h>
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#include <nvgpu/vgpu/vgpu_ivc.h>
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#include <nvgpu/vgpu/vgpu.h>
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#include <hal/fifo/tsg_gk20a.h>
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#include "fifo_vgpu.h"
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#include "channel_vgpu.h"
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#include "tsg_vgpu.h"
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void vgpu_fifo_cleanup_sw(struct gk20a *g)
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{
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u32 i;
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struct nvgpu_fifo *f = &g->fifo;
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for (i = 0U; i < f->max_engines; i++) {
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if (f->host_engines[i] == NULL) {
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continue;
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}
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/*
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* Cast to (void *) to get rid of the constness.
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*/
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nvgpu_kfree(g, (void *)f->host_engines[i]);
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}
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nvgpu_fifo_cleanup_sw_common(g);
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}
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int vgpu_fifo_setup_sw(struct gk20a *g)
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{
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struct nvgpu_fifo *f = &g->fifo;
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struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
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int err = 0;
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nvgpu_log_fn(g, " ");
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if (f->sw_ready) {
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nvgpu_log_fn(g, "skip init");
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return 0;
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}
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err = nvgpu_fifo_setup_sw_common(g);
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if (err != 0) {
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nvgpu_err(g, "fifo sw setup failed, err=%d", err);
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return err;
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}
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#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
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err = nvgpu_channel_worker_init(g);
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if (err) {
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goto clean_up;
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}
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#endif
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f->channel_base = priv->constants.channel_base;
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f->sw_ready = true;
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nvgpu_log_fn(g, "done");
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return 0;
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#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
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clean_up:
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nvgpu_fifo_cleanup_sw_common(g);
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#endif
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return err;
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}
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int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info)
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{
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struct nvgpu_channel *ch = nvgpu_channel_from_id(g, info->chid);
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nvgpu_log_fn(g, " ");
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nvgpu_err(g, "fifo intr (%d) on ch %u",
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info->type, info->chid);
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switch (info->type) {
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case TEGRA_VGPU_FIFO_INTR_PBDMA:
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g->ops.channel.set_error_notifier(ch,
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NVGPU_ERR_NOTIFIER_PBDMA_ERROR);
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break;
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case TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT:
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g->ops.channel.set_error_notifier(ch,
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NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT);
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break;
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case TEGRA_VGPU_FIFO_INTR_MMU_FAULT:
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vgpu_tsg_set_ctx_mmu_error(g, info->chid);
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nvgpu_channel_abort(ch, false);
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break;
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default:
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WARN_ON(1);
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break;
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}
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nvgpu_channel_put(ch);
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return 0;
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}
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