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77f0ab6583
Since gpu server can noew allocate va itself, update_hwpm_ctxsw_mode does not need to fixed map pm ctx anymore. Jira GVSCI-10977 Change-Id: If592c8a2eb6dbfd7d922c79c87871162e9d8d8a4 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2546192 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
105 lines
4.2 KiB
C
105 lines
4.2 KiB
C
/*
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_VGPU_H
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#define NVGPU_GR_VGPU_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_channel;
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struct gr_gk20a;
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#ifdef CONFIG_NVGPU_GRAPHICS
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struct nvgpu_gr_zcull_info;
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struct nvgpu_gr_zcull;
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struct nvgpu_gr_zbc;
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struct nvgpu_gr_zbc_entry;
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struct nvgpu_gr_zbc_query_params;
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#endif
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struct dbg_session_gk20a;
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struct nvgpu_tsg;
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struct vm_gk20a;
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struct nvgpu_gr_ctx;
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struct tegra_vgpu_gr_intr_info;
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struct tegra_vgpu_sm_esr_info;
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struct nvgpu_gr_falcon_query_sizes;
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void vgpu_gr_detect_sm_arch(struct gk20a *g);
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int vgpu_gr_init_ctx_state(struct gk20a *g,
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struct nvgpu_gr_falcon_query_sizes *sizes);
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int vgpu_gr_alloc_global_ctx_buffers(struct gk20a *g);
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void vgpu_gr_free_channel_ctx(struct nvgpu_channel *c, bool is_tsg);
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void vgpu_gr_free_tsg_ctx(struct nvgpu_tsg *tsg);
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int vgpu_gr_alloc_obj_ctx(struct nvgpu_channel *c, u32 class_num, u32 flags);
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u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, struct nvgpu_gr_config *config,
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u32 gpc_index);
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u32 vgpu_gr_get_max_fbps_count(struct gk20a *g);
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u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g);
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u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g);
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#ifdef CONFIG_NVGPU_GRAPHICS
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int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct nvgpu_channel *c,
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u64 zcull_va, u32 mode);
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int vgpu_gr_get_zcull_info(struct gk20a *g,
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struct nvgpu_gr_config *gr_config,
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struct nvgpu_gr_zcull *zcull,
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struct nvgpu_gr_zcull_info *zcull_params);
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int vgpu_gr_add_zbc(struct gk20a *g, struct nvgpu_gr_zbc *zbc,
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struct nvgpu_gr_zbc_entry *zbc_val);
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int vgpu_gr_query_zbc(struct gk20a *g, struct nvgpu_gr_zbc *zbc,
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struct nvgpu_gr_zbc_query_params *query_params);
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#endif
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int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g,
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struct nvgpu_tsg *tsg, bool enable);
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int vgpu_gr_set_sm_debug_mode(struct gk20a *g,
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struct nvgpu_channel *ch, u64 sms, bool enable);
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int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
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u32 gr_instance_id, struct nvgpu_tsg *tsg, u32 mode);
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int vgpu_gr_clear_sm_error_state(struct gk20a *g,
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struct nvgpu_channel *ch, u32 sm_id);
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int vgpu_gr_suspend_contexts(struct gk20a *g,
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struct dbg_session_gk20a *dbg_s,
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int *ctx_resident_ch_fd);
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int vgpu_gr_resume_contexts(struct gk20a *g,
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struct dbg_session_gk20a *dbg_s,
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int *ctx_resident_ch_fd);
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int vgpu_gr_init_sm_id_table(struct gk20a *g,
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struct nvgpu_gr_config *gr_config);
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int vgpu_gr_update_pc_sampling(struct nvgpu_channel *ch, bool enable);
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void vgpu_gr_init_cyclestats(struct gk20a *g);
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int vgpu_gr_set_preemption_mode(struct nvgpu_channel *ch,
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u32 graphics_preempt_mode, u32 compute_preempt_mode,
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u32 gr_instance_id);
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int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info);
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void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
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struct tegra_vgpu_sm_esr_info *info);
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int vgpu_init_gr_support(struct gk20a *g);
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u32 vgpu_gr_get_max_gpc_count(struct gk20a *g);
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u32 vgpu_gr_get_gpc_count(struct gk20a *g);
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u32 vgpu_gr_get_gpc_mask(struct gk20a *g);
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#ifdef CONFIG_NVGPU_DEBUGGER
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u64 vgpu_gr_gk20a_tpc_enabled_exceptions(struct gk20a *g);
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int vgpu_gr_set_mmu_debug_mode(struct gk20a *g,
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struct nvgpu_channel *ch, bool enable);
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#endif
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#endif /* NVGPU_GR_VGPU_H */
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