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bdf4f1eb96
Add hals get_cntr_sysclk_source, get_cntr_xbarclk_source to get counter clock sources as they can differ for different chips. Jira NVGPU-5435 Change-Id: I3206f12baac075803ea4412766db60c9b55c6cc5 Signed-off-by: shashank singh <shashsingh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2366047 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
62 lines
2.2 KiB
C
62 lines
2.2 KiB
C
/*
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* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef CLK_TU104_H
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#define CLK_TU104_H
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#include <nvgpu/lock.h>
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#include <nvgpu/gk20a.h>
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#define CLK_NAME_MAX 24
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#define CLK_MAX_CNTRL_REGISTERS 2
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struct namemap_cfg {
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u32 namemap;
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u32 is_enable;
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u32 is_counter;
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struct gk20a *g;
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struct {
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u32 reg_ctrl_addr;
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u32 reg_ctrl_idx;
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u32 reg_cntr_addr[CLK_MAX_CNTRL_REGISTERS];
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} cntr;
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u32 scale;
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char name[CLK_NAME_MAX];
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};
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u32 tu104_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c);
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int tu104_init_clk_support(struct gk20a *g);
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u32 tu104_crystal_clk_hz(struct gk20a *g);
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u32 tu104_clk_get_cntr_xbarclk_source(struct gk20a *g);
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u32 tu104_clk_get_cntr_sysclk_source(struct gk20a *g);
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unsigned long tu104_clk_measure_freq(struct gk20a *g, u32 api_domain);
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void tu104_suspend_clk_support(struct gk20a *g);
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int tu104_clk_domain_get_f_points(
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struct gk20a *g,
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u32 clkapidomain,
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u32 *pfpointscount,
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u16 *pfreqpointsinmhz);
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unsigned long tu104_clk_maxrate(struct gk20a *g, u32 api_domain);
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void tu104_get_change_seq_time(struct gk20a *g, s64 *change_time);
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void tu104_change_host_clk_source(struct gk20a *g);
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#endif /* CLK_TU104_H */
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